Reconfigurable Amplifier Load-Line Control for Lower Current Draw

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Solution Overview

Problem

Current amplifiers in wireless transceivers consume significant power, leading to reduced battery life in portable devices, and existing methods to reduce power consumption, such as using output matching networks, are impractical due to size and cost constraints.

Innovation Solution

The amplifier is reconfigured to adjust its load line impedance by selectively enabling or disabling transistors and using complementary transistors to inject half-cycle delayed current, reducing current draw without adding expensive hardware like inductors or transformers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If amplifier power consumption is reduced to extend battery life, then duration of action is improved, but power delivery capability deteriorates

Engineering Contradiction:
Improvebattery lifeVSAvoidpower delivery capability
Core Design Contradiction:
Duration of action of moving objectVSPower

Solution Approach 1:

The amplifier implements dynamic reconfiguration between different operating modes (Class AB and Class C) based on signal conditions. The circuit selectively enables or disables specific transistor pairs and adjusts biasing conditions, allowing the amplifier to adapt its power consumption and efficiency characteristics in real-time while maintaining adequate power delivery capability when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The amplifier changes its operating parameters by adjusting the effective load line impedance through selective transistor activation. By modifying which transistors are active and how they are biased, the amplifier alters its power consumption characteristics and efficiency without requiring additional hardware components, thereby extending battery life while preserving power delivery capability.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If output matching networks are added to reduce power consumption, then use of energy is improved, but device complexity and size increase

Engineering Contradiction:
Improvepower consumption efficiencyVSAvoidcircuit complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The existing transistor pairs in the amplifier are made multi-functional by selectively enabling them for different purposes. The same physical transistors serve both as amplifying elements in Class AB mode and as active load elements in Class C mode, eliminating the need for separate matching networks or additional hardware components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The amplifier creates a virtual matching network effect by using complementary transistor pairs that replicate the impedance transformation function traditionally provided by physical matching networks. This software-defined or circuit-defined approach achieves the same power efficiency benefits without adding physical components.

Inventive Principle:
Principle #26Copying

3Use of energy by moving object

If amplifier reconfiguration is implemented to adjust load line impedance, then power consumption is reduced, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit configuration complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The amplifier merges the functions of multiple transistor pairs into a single reconfigurable circuit architecture. By combining Class AB and Class C operating modes within the same physical circuit and using shared components, the design achieves power consumption reduction without proportionally increasing complexity, as the same hardware serves multiple functions.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10644650B2Amplifier configuration for load-line enhancement
Publication Date: 2020.05.05 QUALCOMM INC
  • US10644650B2 patent drawing
  • US10644650B2 patent drawing
  • US10644650B2 patent drawing

AI summary

Amplifier configuration for load-line enhancement is described herein. In some implementations, an apparatus includes an amplifier. The amplifier includes at least one plus transistor stack, at least one minus transistor stack, and at least one inductor. The at least one plus transistor stack is coupled to a plus amplifier node and a plus input node. The at least one minus transistor stack is coupled to a minus amplifier node and a minus input node. The at least one inductor is coupled between the plus amplifier node and the minus amplifier node, with the at least one inductor including an inter-inductor node. The amplifier also includes a minus power switch coupled between the minus amplifier node and one or more supply voltages and an inductor power switch coupled between the inter-inductor node and at least one supply voltage.