Signal-Dependent Amplifier Mode Switching for Low-Power Efficiency

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Solution Overview

Problem

Class-D amplifiers with closed-loop designs suffer from low efficiency at small output power due to high quiescent current, degrading from 90% at 2.0 mW to 10% at 0.1 mW, making them inefficient for low-power applications like cellphones and headphones.

Innovation Solution

The amplifier switches between closed-loop and open-loop modes based on input signal strength, enabling or disabling analog and digital signal processing circuits to maintain efficiency across power levels, with a startup circuit to minimize switching glitches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If closed-loop design is used, then performance (THD, PSRR, jitter immunity) is improved, but quiescent current increases and efficiency degrades at small output power

Engineering Contradiction:
ImproveperformanceVSAvoidefficiency
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The amplifier dynamically switches between closed-loop and open-loop modes based on the power level of the input signal. When the input signal power exceeds a threshold, the closed-loop mode is activated for optimal performance; when below the threshold, the open-loop mode is activated for efficient operation. This dynamic adaptation resolves the contradiction by adjusting the operating mode according to real-time signal conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters of the amplifier by switching between two distinct operating modes (closed-loop and open-loop). The mode selection is controlled by comparing the power level of the input signal against a predetermined threshold, thereby changing the system's parameters (loop configuration, circuit enablement) to match the required performance-efficiency balance at different power levels.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If closed-loop mode is used at small output power, then performance is maintained, but quiescent power consumption increases significantly

Engineering Contradiction:
ImproveperformanceVSAvoidquiescent power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The system applies partial action by selectively enabling only the necessary circuit blocks based on operating conditions. At low power levels, the feedback path and certain analog circuit blocks are disabled, reducing quiescent power consumption while maintaining sufficient performance through the open-loop digital signal processing path. This partial activation of circuitry resolves the contradiction between maintaining performance and reducing standby power consumption.

Inventive Principle:
Principle #16Partial or excessive action

3Use of energy by moving object

If mode switching is implemented, then efficiency is improved across power levels, but circuit complexity increases

Engineering Contradiction:
ImproveefficiencyVSAvoidcircuit complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The amplifier is segmented into distinct functional paths: an open-loop digital signal processing path and a closed-loop analog signal processing path with feedback. Each path is independently controllable through mode selection circuitry that enables or disables specific blocks based on input signal power levels. This segmentation allows efficient switching between modes without requiring complete redesign of the entire system, thereby managing complexity while achieving efficiency improvements.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3813256B1Amplifier with signal dependent mode operation
Publication Date: 2024.08.07 MEDIATEK INC
  • EP3813256B1 patent drawingFigure 1
  • EP3813256B1 patent drawingFigure 2
  • EP3813256B1 patent drawingFigure 3

AI summary

The present invention provides an amplifier including a DAC, an analog signal processing circuit, a digital signal processing circuit, a signal detector and a driving stage is disclosed. The DAC is configured to perform a digital-to-analog conversion operation on a digital input signal to generate an analog input signal. The analog signal processing circuit is configured to generate a first processed signal according to the analog input signal and a feedback signal. The digital signal processing circuit is configured to process the digital input signal to generate a second processed signal. The signal detector is configured to detect strength of the digital input signal to generate a mode selection signal. The driving stage is configured to refer to the mode selection signal to receive one of the first processed signal and the second processed signal to generate an output signal, wherein the feedback signal is generated by the output signal.