Analog Amplifier Offset Cancellation With Binary-Weighted Current Sources
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Solution Overview
Problem
Existing analog amplifiers face challenges in completely eliminating DC offset voltage, which leads to asymmetry and mismatch in differential outputs, affecting bit-error-rate performance and requiring large chip area for low-frequency cutoff compensation.
Innovation Solution
The proposed solution involves a system with a biasing circuit and current sources to adjust the DC voltage at the input node for offset compensation, using a binary-weighted current source configuration to minimize chip area and achieve precise offset cancellation, along with a folded active inductor load to extend circuit bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional error amplifier with low-pass RC filters is used for offset cancellation, then DC offset voltage is reduced, but chip area increases due to large resistance and capacitance values required for low-frequency cutoff
Solution Approach 1:
The patent changes the operating parameters by using binary-weighted current sources with selectable connections to the inverting input, replacing the traditional continuous low-pass RC filter approach. This allows precise DC offset cancellation through digital-controlled current summation, achieving the desired low-frequency cutoff without requiring large physical R and C values that would consume excessive chip area.
Solution Approach 2:
The offset cancellation is achieved by segmenting the current sources into binary-weighted units (I, 2I, 4I, 8I) that can be independently switched. This segmentation allows the system to achieve fine-grained control over the cancellation current while using smaller individual current source elements, reducing the overall area compared to a single large error amplifier and RC network.
2Measurement precision
If finite gain error amplifier is used for offset compensation, then offset voltage is reduced, but residual offset remains due to limited gain and error amplifier offset voltage
Solution Approach 1:
The patent implements a feedback mechanism where the output of the main amplifier is fed back through the biasing circuit to the inverting input. The binary-weighted current sources are controlled by feedback signals that adjust the cancellation current based on the detected output offset, creating a closed-loop system that continuously minimizes residual offset voltage despite finite gain limitations.
Solution Approach 2:
The system performs self-calibration by automatically adjusting the binary-weighted current source connections to cancel its own offset voltage. The feedback-controlled switching mechanism enables the amplifier to self-correct its offset without requiring external calibration equipment, reducing residual offset through autonomous operation.
Data Source
AI summary
An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier