Amplifier Output Stage Settling Time Reduction
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Solution Overview
Problem
Existing multi-stage amplifiers, such as low-dropout (LDO) regulators, face limitations in achieving a balance between stability and bandwidth during load transients, particularly due to the large load capacitance formed by the pass device, which restricts the settling speed of the output voltage.
Innovation Solution
The output stage of the amplifier is configured with a first input transistor, a diode transistor in series, a pass device forming a current mirror, and additional transistors to control voltage levels and sink or source charge currents, utilizing a replica node and buffer transistor to rapidly react to load transients and reduce settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the pass device is used to provide output current, then the output current capability is improved, but the settling time increases due to large load capacitance
Solution Approach 1:
The buffer transistor is prepared in advance to provide charge current to the gate node of the pass device when load transients occur. The replica node detects voltage changes beforehand, triggering the buffer transistor to preemptively charge or discharge the gate capacitance, thereby reducing settling time without compromising output current capability
Solution Approach 2:
The buffer transistor acts as an intermediary between the control circuitry and the pass device gate. It isolates the gate node from direct control signals and provides additional charge current through its own gate-drain connection, enabling faster response to load transients while maintaining the pass device's current delivery capability
2Speed
If the bandwidth is increased to respond rapidly to load transients, then the response speed is improved, but the stability deteriorates
Solution Approach 1:
The replica node provides feedback about voltage changes at the gate node to the buffer transistor control. When the gate node voltage deviates due to load transients, the replica node detects this and triggers the buffer transistor to correct the voltage, providing automatic stabilization while enabling fast response
Solution Approach 2:
The buffer transistor dynamically changes the charge current parameter supplied to the gate node based on load transient conditions. During transients, it provides high charge current for fast response; during steady state, it remains inactive, maintaining stability. This dynamic parameter adjustment resolves the speed-stability tradeoff
3Loss of time
If additional transistors are added to control voltage levels and reduce settling time, then the settling speed is improved, but the device complexity increases
Solution Approach 1:
The buffer transistor performs multiple functions: it provides charge current to the gate node, acts as a voltage amplifier, and serves as a current source/sink. The replica node simultaneously monitors gate voltage and controls the buffer transistor. This multi-functionality reduces the need for separate dedicated components, limiting complexity increase
Solution Approach 2:
The buffer transistor combines the functions of a voltage amplifier and a charge pump into a single device. Its gate-drain connection merges the control signal path with the charge current path, eliminating the need for separate control circuits and reducing overall complexity while achieving fast settling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the settling time of the output voltage while maintaining stability, allowing the amplifier to respond quickly to load transients with minimal additional current consumption, enhancing both speed and stability.
Implementation Method 1
sinking or sourcing a charge current at the gate node based on voltage levels at the gate node and at the replica node
Implementation Method 2
a pass device forming a current mirror with a diode transistor
Data Source
Figure 1a~1b
Figure 2
Figure 3a
AI summary
The present document relates to amplifiers, notably multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. An amplifier (100, 200) comprising an output stage (103) for providing an output current (106) at an output voltage (306), in dependence of an input voltage at a stage input node (262) of the output stage (103), is described. The output stage (103) comprises a first input transistor (270); wherein a gate of the first input transistor (270) is coupled to the stage input node (262) of the output stage (103). Furthermore, the output stage (103) comprises a first diode transistor (271); wherein the first diode transistor (271) is arranged in series with the input transistor (270). In addition, the output stage (103) comprises a pass device (201) configured to provide the output current (106) at the output voltage (306); wherein the first diode transistor (271) and the pass device (201) form a current mirror; wherein a midpoint between the first input transistor (270) and the first diode transistor (271) is coupled to a gate node (308) of the pass device (201). Furthermore, the output stage (103) comprises a second input transistor (370); wherein a gate of the second input transistor (370) is coupled to the stage input node (262) of the output stage (103); wherein the second input transistor (370) is configured to control a voltage level at a replica node (398), in dependence of the input voltage. In addition, the output stage (103) comprises a buffer transistor (312); wherein a gate of the buffer transistor (312) is coupled to the replica node (398) and wherein an input node of the buffer transistor (312) is coupled to the gate node (308), such that the buffer transistor (312) is configured to sink or source a charge current (383, 384) at the gate node (308), subject to the voltage level at the replica node (398) and the voltage level at the gate node (308).