Semiconductor Amplifier Parasitic Capacitance Reduction
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Solution Overview
Problem
Modern semiconductor amplifiers face inefficiencies due to high parasitic capacitance, which affects their power conversion efficiency and frequency response.
Innovation Solution
The design incorporates additional dielectric filled trench isolation walls and electrically floating peripheral semiconductor regions to reduce lateral parasitic capacitance, while also addressing parasitic buried layer leakage through strategic doping and layer arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional amplifier designs are used, then device complexity is reduced, but parasitic capacitance increases leading to lower efficiency
Solution Approach 1:
The amplifier design segments the collector region into multiple isolated sections using dielectric-filled trench isolation walls. Each transistor cell is laterally surrounded by isolation walls that extend through the collector region to the substrate, creating electrically isolated segments that reduce parasitic capacitance between adjacent collector regions while maintaining individual transistor functionality.
Solution Approach 2:
Dielectric materials are introduced as intermediary substances between adjacent collector regions. The dielectric-filled trenches act as electrical insulators and mediators that prevent direct capacitive coupling between neighboring collectors, thereby reducing parasitic capacitance without requiring increased physical spacing between devices.
2Area of stationary object
If collector regions are placed closer together to increase density, then device area is reduced, but parasitic capacitance between collectors increases
Solution Approach 1:
The isolation structure extends vertically through the collector region depth rather than relying solely on horizontal spacing. By implementing isolation walls that penetrate from the upper surface through the collector to the substrate, the solution addresses parasitic capacitance in the vertical dimension, enabling closer horizontal placement of collector regions without increasing parasitic coupling.
Solution Approach 2:
The dielectric isolation is applied locally at specific interfaces between adjacent collector regions rather than uniformly throughout the entire device. The isolation walls are strategically positioned at lateral boundaries where parasitic capacitance occurs, providing targeted reduction of parasitic effects only where needed while maintaining optimal collector spacing for high density.
Data Source
AI summary
A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.