Amplifier Circuit Reset Mechanism for Interlaced Input Signal Integrity
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Solution Overview
Problem
In complementary input amplifiers, interlaced input signals are affected by residual electrical charges from parasitic capacitors, leading to inter-symbol interference, which is a challenge in low power consumption designs for portable electronic products and 5G technology.
Innovation Solution
An amplifier circuit with a reset mechanism is designed, featuring pairs of upper-half and lower-half branches with P-type and N-type transistors respectively, where transistor groups perform differential and reset signal receiving processes in an interlaced manner, with AC grounding to clear electrical charges from parasitic capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If interlaced input mode is used in complementary input amplifier, then power consumption is reduced, but inter-symbol interference occurs due to residual electrical charges
Solution Approach 1:
The amplifier circuit is divided into multiple transistor groups (first transistor group, second transistor group, etc.) that operate in an interlaced manner. Each transistor group processes different input signals at different time intervals, allowing residual charges to dissipate between processing cycles and preventing inter-symbol interference while maintaining low power consumption
Solution Approach 2:
The transistor groups perform differential signal receiving processes in periodic time intervals rather than simultaneously. The first transistor group receives signals during one time interval, then the second transistor group receives signals during the next time interval, creating a periodic operation pattern that allows parasitic capacitors to discharge between cycles
2Reliability
If reset mechanism is added to clear residual charges, then signal integrity is improved, but circuit complexity increases
Solution Approach 1:
The circuit uses the natural alternating operation of transistor groups to automatically reset parasitic capacitors. When one transistor group is inactive, its associated parasitic capacitors naturally discharge through the inactive transistors, providing self-reset functionality without requiring external reset circuits or additional control mechanisms
Solution Approach 2:
The reset function is merged into the normal operation of the transistor groups. The same transistors that process differential signals also serve as discharge paths for parasitic capacitors during their inactive periods, combining signal processing and reset functions into a single integrated mechanism
Data Source
AI summary
The present disclosure discloses an amplifier circuit having reset mechanism. A pair of upper-half branches are electrically coupled between a first supply voltage and a pair of differential output terminals, are symmetrical and each includes at least one P-type transistor. A pair of lower-half branches are electrically coupled between the pair of differential output terminals and a second supply voltage, are symmetrical and each includes at least one N-type transistor. The P-type transistors and the N-type transistors are categorized into transistor groups that perform differential signal receiving process in turn in an interlaced manner under an interlaced input mode and perform reset signal receiving process to be turned on and be AC grounded when the differential signal receiving process is not performed such that the differential output terminals generate differential outputs.