Differential Amplifier Sub-Current Sources for Slew Rate Boost
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Solution Overview
Problem
Conventional differential amplifier circuits face limitations in slew rate due to restricted charging and discharging speeds of capacitors and gate voltage variations, leading to increased power consumption when transistors are turned on in steady-state conditions.
Innovation Solution
A differential amplifier circuit design incorporating P-type and N-type differential input units, current mirror circuits, and sub-current sources with specific transistor configurations to control output voltage slew rate, reducing steady-state current consumption and enhancing slew rate by managing control outputs and current flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate-source voltage or source-gate voltage of transistors M15, M16 in steady state is greater than threshold voltage to turn on transistors M18, M19 for providing temporary-state current, then the slew rate of output voltage is improved, but the steady-state current increases leading to increased power consumption
Solution Approach 1:
The patent implements dynamic control of transistor M18 and M19 through separate control signals (first control signal from P-type current mirror circuit and second control signal from N-type current mirror circuit). These transistors are turned on only during transient states when voltage variations occur, and turned off during steady state, making the current supply dynamic rather than static. This resolves the contradiction by providing high current only when needed for slew rate improvement while minimizing steady-state current consumption.
Solution Approach 2:
The control signals for transistors M18 and M19 are generated automatically by the P-type and N-type current mirror circuits based on the differential input voltages. When voltage variations occur at the differential inputs, the current mirror circuits self-adjust to produce control signals that turn on the respective transistors. This self-service mechanism eliminates the need for external control logic and ensures automatic optimization of power consumption based on operational conditions.
2Speed
If transistors M18, M19 are turned on to provide temporary-state current for rapid capacitor charging and discharging, then the charging and discharging speeds are improved, but the steady-state current increases
Solution Approach 1:
The patent employs periodic action by controlling transistors M18 and M19 to operate only during transient periods when voltage changes occur, rather than continuously. The P-type and N-type current mirror circuits generate control signals that activate these transistors temporarily during voltage transitions and deactivate them during steady state. This periodic operation provides rapid charging and discharging speeds when needed while minimizing steady-state current consumption.
Solution Approach 2:
The patent changes the operational parameters of transistors M18 and M19 dynamically by controlling their gate voltages through the current mirror circuits. During transient states, the control signals adjust the gate voltages to turn on these transistors, enabling rapid current flow for capacitor charging and discharging. During steady state, the control signals adjust the gate voltages to turn off these transistors, reducing current consumption. This parameter change approach resolves the contradiction between speed and current quantity.
Data Source
AI summary
A differential amplifier circuit includes: P-type and N-type differential input units outputting respectively first and second outputs in response to first and second input voltages; a P-type current mirror circuit driven by the second output; an N-type current mirror circuit driven by the first output; an output unit outputting an output voltage in response to control outputs from the P-type and N-type current mirror circuits; a first sub-current source including first and second P-type transistors connected in series; and a second sub-current source including first and second N-type transistors connected in series. Control ends of the second P-type and second N-type transistors receive the control outputs from the P-type and N-type current mirror circuits, respectively. Control ends of the first P-type and first N-type transistors are coupled to a common node between the first and second P-type transistors, and a common node between the first and second N-type transistors, respectively.