Amplifier Module Via Layout for Heat Dissipation and Mounting Stability
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Solution Overview
Problem
The challenge is to enhance heat dissipation in power amplifier modules for wireless communication terminals, particularly in 5G systems, where increased output power generates more heat, degrading semiconductor integrated circuit characteristics, and existing methods to increase via conductors or their cross-sectional area are limited by manufacturing constraints, affecting the yield of flip-chip mounting processes.
Innovation Solution
An amplifier module design featuring a multilayer board with a larger area first common via conductor in the shallow region, a thicker common bump, and a heat conduction path that expands deeper, reducing thermal resistance and allowing stable mounting by adjusting bump heights to maintain even surfaces, thereby improving heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the number of via conductors is increased to improve heat dissipation, then thermal resistance decreases, but manufacturing constraints prevent further increase
Solution Approach 1:
Multiple via conductors (first, second, third common via conductors) are merged into a single integrated heat conduction structure beneath the integrated circuit device, combining their heat dissipation functions while occupying a compact space that satisfies manufacturing constraints
Solution Approach 2:
The via conductors are arranged in a nested configuration where the second common via conductor is positioned deeper than the first, and the third common via conductor connects to the lower surface, creating a multi-layered heat conduction path that maximizes thermal dissipation within the board thickness
2Temperature
If the horizontal cross section of via conductor is enlarged to reduce thermal resistance, then heat dissipation improves, but the upper surface height varies causing mounting yield to decrease
Solution Approach 1:
The via conductors are designed with different cross-sectional areas at different locations: the first common via conductor has a larger cross section at its upper surface to reduce thermal resistance, while the second and third via conductors have smaller cross sections, creating a gradient structure that balances heat dissipation with surface height control
Solution Approach 2:
The heat conduction path is extended into the depth dimension by arranging via conductors at different depths (first, second, and third common via conductors), allowing thermal resistance reduction without requiring excessive lateral expansion that would cause surface height variation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces thermal resistance and maintains stable mounting of integrated circuit devices, enhancing heat dissipation and preventing temperature rise while ensuring stable integration, even with increased output power.
Implementation Method 1
use this via conductor as a heat conduction path. To reduce the thermal resistance of this heat conduction path
Implementation Method 2
a common bump, an input bump, and an output bump that connect the multilayer board and the integrated circuit device
Data Source
AI summary
An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.