Amplitude Modulation Circuit With Triode MOS for Low Distortion

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Solution Overview

Problem

Existing amplitude modulation circuits suffer from low linearity, leading to increased third-order intermodulation distortion and incorrect signal detection, particularly when modulating signals with close frequency components.

Innovation Solution

An amplitude modulation circuit is designed with a specific configuration including bipolar transistors, resistive elements, and a Metal-Oxide-Semiconductor (MOS) transistor operating in a non-saturated region, with a drain-source resistance larger than the resistive elements, to enhance linearity and reduce distortion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional amplifier circuit is used for amplitude modulation, then the circuit structure is simple, but the linearity is poor causing third-order intermodulation distortion

Engineering Contradiction:
ImprovelinearityVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The circuit is divided into two parallel branches: a first branch with a first transistor and first resistive element for processing one signal component, and a second branch with a second transistor and second resistive element for processing another signal component. This segmentation allows each branch to contribute to linear amplitude modulation while maintaining manageable circuit complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first MOS transistor is configured to operate specifically in a non-saturated region (triode region) with its resistance being larger than the resistive elements, creating a localized region of high linearity. This local quality improvement in the MOS transistor configuration enhances overall circuit linearity without requiring complete redesign of all circuit components.

Inventive Principle:
Principle #3Local quality

2Reliability

If amplitude modulation is performed with low linearity, then the circuit operation is simple, but third-order intermodulation distortion increases causing incorrect signal detection

Engineering Contradiction:
Improvesignal detection accuracyVSAvoidtransistor configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The first MOS transistor acts as an intermediary element between the input signals and the output, operating in the non-saturated region to provide a linear resistance that mediates the amplitude modulation process. This intermediary configuration ensures accurate signal detection by preventing distortion while integrating smoothly with the existing transistor structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the MOS transistor resistance is made larger than the resistive elements, then linearity is improved, but the voltage gain may be reduced

Engineering Contradiction:
ImprovelinearityVSAvoidvoltage gain
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The circuit operates by changing the resistance parameter of the MOS transistor dynamically as it switches between different resistance states during the amplitude modulation process. By configuring the MOS transistor to operate in the non-saturated region with resistance larger than the resistive elements, the circuit achieves optimal linearity while maintaining sufficient voltage gain through parameter optimization.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11588476B2Amplitude modulation circuit and semiconductor integrated circuit for optical communication system
Publication Date: 2023.02.21 SUMITOMO ELECTRIC INDUSTRIES LTD
  • US11588476B2 patent drawing
  • US11588476B2 patent drawing
  • US11588476B2 patent drawing

AI summary

An amplitude modulation circuit includes: first, second, and third input terminals; first and second output terminals; a current source; first and second transistors including a base electrically connected to the first and second input terminals, a collector electrically connected to the first and second output terminals, and an emitter electrically connected to a grounding terminal via the current source; first and second resistive elements electrically connected between the first and second output terminals and a power line; and a first MOS transistor including a drain connected to the first output terminal, a source connected to the second output terminal, and a gate connected to the third input terminal. The MOS transistor is configured to operate in a non-saturated region, and a resistance between the source and the drain of the MOS transistor is larger than resistances of the first and second resistive elements.