Amplitude Sweep Generator Using Time-Modulated Clock Compensation

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Solution Overview

Problem

Existing signal generators face challenges in generating amplitude sweeps with high accuracy and linearity while maintaining low circuit complexity, particularly in biomedical applications like biomedical radar systems.

Innovation Solution

A signal generator with a shift register and clock signal generator that controls activation of control components in parallel, using a time-modulated clock signal to compensate for non-linearity, reducing circuit complexity and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If switchable parallel power amplifier units or switchable resistors are used to generate amplitude sweeps, then the amplitude sweep can be generated, but the circuit complexity and power consumption increase

Engineering Contradiction:
Improveamplitude sweep accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The signal generator is divided into multiple parallel control components (power amplifier units or current sources), each controlled by individual bits of a shift register. This segmentation allows independent control of each component to achieve precise amplitude sweeps while maintaining modular circuit architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The clock signal is dynamically modulated in time to compensate for non-linear amplitude dependence. By varying the clock signal timing rather than using fixed intervals, the system achieves linear amplitude sweeps despite the intrinsic non-linear relationship between the number of activated control components and output amplitude.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If switchable parallel power amplifier units or switchable resistors are used to generate amplitude sweeps, then the amplitude sweep can be generated, but the power consumption increases

Engineering Contradiction:
Improveamplitude sweep accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

Instead of activating all control components simultaneously or using full-power amplifiers continuously, the system activates only the necessary number of control components at each time step to achieve the desired amplitude. This partial activation reduces power consumption while maintaining sweep accuracy through selective component engagement.

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If a simple shift register with parallel control components is used, then the circuit complexity is reduced, but the amplitude sweep linearity deteriorates due to intrinsic non-linear dependence

Engineering Contradiction:
Improvecircuit complexityVSAvoidamplitude sweep linearity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The clock signal parameters (timing intervals) are changed dynamically to compensate for the non-linear amplitude response. By adjusting the time between clock edges based on the desired amplitude profile, the system achieves linear amplitude sweeps despite the non-linear intrinsic dependence of amplitude on the number of activated control components.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3667913B1Amplitude sweep generator and method
Publication Date: 2026.01.21 STICHTING IMEC NEDERLAND
  • EP3667913B1 patent drawingFigure 1a
  • EP3667913B1 patent drawingFigure 1b
  • EP3667913B1 patent drawingFigure 2a~2c

AI summary

A signal generator (2) is configured to generate a signal with an amplitude sweep, the signal generator having circuitry comprising: a set of control components (8, 108), each control component of the set of control components being arranged to be switchably activated in parallel in the circuitry so that an amplitude of the signal has an intrinsic dependence on the number of the control components activated; a shift register (5) controllable by a clock line and comprising a number of bits (6), each bit (6) of the number of bits (6) controlling activation of a respective control component of the set of control components (8, 108) so that the control components (8, 108) are arranged to be activated or de-activated in a pre-determined order by shifting, respectively, activation or de-activation bits into the shift register, wherein the shifting is paced by the clock line; and a clock signal generator (4) configured to output a clock signal with a time modulation on the clock line.