Analog Assertion Publication and Re-use via GUI
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current analog circuit design tools lack effective methods for managing and reusing assertion-related information, particularly for analog and mixed-signal circuit designs, due to the complexity of text-based assertion languages and the absence of interactive publication and re-use flows.
Innovation Solution
A graphical user interface (GUI) based system and method for creating, verifying, formalizing, and publishing analog assertions, allowing users to capture and parameterize assertions for re-use, and store them in a library accessible to other designers, enabling point-and-click interaction and instantiation without requiring code writing skills.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If text-based assertion languages (PSL/SVA) are used for analog circuit verification, then verification capability is improved, but ease of operation deteriorates due to the complexity of writing and managing assertions
Solution Approach 1:
The patent introduces a graphical user interface (GUI) as an intermediary between the designer and the text-based assertion languages. The GUI provides a visual environment where designers can create, edit, and manage assertions without directly writing PSL/SVA code, thus maintaining verification capability while significantly improving ease of operation.
Solution Approach 2:
The patent replaces the mechanical process of manually writing and editing text-based assertions with an automated graphical interface system. The GUI automatically generates and manages assertion code based on user interactions, eliminating the need for designers to directly manipulate text-based assertion languages.
2Productivity
If assertion management tools are developed for analog design, then productivity is improved through re-use, but device complexity increases due to new publication and re-use flows
Solution Approach 1:
The patent merges the assertion creation, verification, and publication processes into a unified graphical interface environment. By combining these previously separate functions into a single integrated system, the patent simplifies the overall publication flow while enabling efficient assertion re-use across different designs.
Solution Approach 2:
The patent creates a universal assertion management system that handles multiple functions (creation, verification, publication, and re-use of assertions) through a single graphical interface. This multi-functional approach reduces the complexity of individual processes while maintaining comprehensive assertion management capabilities.
3Adaptability or versatility
If verification units are stored in separate files from circuit designs, then modularity is improved, but ease of operation deteriorates due to the need to manage separate verification and design files
Solution Approach 1:
The patent combines the management of circuit designs and verification units into a single graphical interface environment. While verification units remain as separate modular entities, the GUI provides a unified view and management mechanism that eliminates the need for designers to manually handle separate files, thus maintaining modularity while improving ease of operation.
Data Source
AI summary
A system and method for managing analog assertion publication and re-use for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to create, verify, formalize, and publish an analog assertion for a circuit design for subsequent re-use with another circuit design. Embodiments enable analog assertion handling while simultaneously depicting a circuit design in a schematic and/or layout editor window. Embodiments capture referenced circuit objects and parameterize the assertion for numerical values and connectivity. A designer may publish the assertion and annotate it with descriptive metadata, possibly with other assertions of related functionality, to a library accessible by users of analog design and verification tools. Another designer may re-use the assertion by searching for and selecting a relevant published assertion, instantiating and binding the selected assertion to specific elements of a second circuit design, and verify the assertion for the second circuit design.