Analog Data Bit Status Detector for Flash Memory
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Solution Overview
Problem
Existing flash memory technologies require complex logic circuit designs and large circuit areas to accurately calculate the number of bits at logic level 0 in data signals, making them inefficient in terms of circuit complexity and space usage.
Innovation Solution
A data bit status detector is implemented in an analog circuit form, comprising a sense amplifying circuit, a data receiving circuit, and a reference circuit, which senses and amplifies impedance differences to determine the logic level status of data signals, thereby simplifying circuit design and reducing the required circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a bit counter circuit in logic circuit form is used to calculate the number of bits at logic level 0, then accurate bit status detection is achieved, but circuit complexity and circuit area increase
Solution Approach 1:
The patent replaces the logic circuit form bit counter with an analog circuit form data bit status detector. The analog detector uses sense amplifying circuits to detect impedance changes caused by different numbers of logic 0 bits, converting the digital bit counting problem into an analog impedance measurement problem. This substitution significantly reduces circuit complexity while maintaining detection accuracy.
Solution Approach 2:
The patent changes the measurement parameter from digital bit counting to analog impedance detection. By using sense amplifying circuits to measure impedance variations in response to different bit patterns, the system transforms the discrete digital measurement into a continuous analog measurement, thereby simplifying the overall circuit architecture.
2Measurement precision
If a bit counter circuit in logic circuit form is used to calculate the number of bits at logic level 0, then accurate bit status detection is achieved, but circuit area increases
Solution Approach 1:
The patent replaces the logic circuit form bit counter with an analog circuit form data bit status detector. The analog detector uses sense amplifying circuits to detect impedance changes caused by different numbers of logic 0 bits, converting the digital bit counting problem into an analog impedance measurement problem. This substitution significantly reduces circuit complexity while maintaining detection accuracy.
Solution Approach 2:
The sense amplifying circuit serves multiple functions: it detects impedance changes, amplifies the differential signal, and determines bit status information. By making the sense amplifying circuit multi-functional, the patent eliminates the need for separate logic circuit components, thereby reducing overall circuit area.
3Measurement precision
If complicated logic circuit design is used to constitute the bit counter circuit, then accurate calculation of logic level 0 bits is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent replaces the logic circuit form bit counter with an analog circuit form data bit status detector. The analog detector uses sense amplifying circuits to detect impedance changes caused by different numbers of logic 0 bits, converting the digital bit counting problem into an analog impedance measurement problem. This substitution significantly reduces circuit complexity while maintaining detection accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces circuit complexity and area, leading to more efficient use of resources and lower costs, while maintaining accurate bit status detection for programming operations in flash memory systems.
Implementation Method 1
The sense amplifying circuit senses and amplifies a difference between a first impedance on the first sense input end and a second impedance on the second sense input end to generate a sensing output signal
Data Source
AI summary
A memory circuit and a data bit status detector thereof are provided. The data bit status detector includes a sense amplifying circuit, a data receiving circuit, and a reference circuit. The sense amplifying circuit has a first sense input end and a second sense input end. The sense amplifying circuit senses and amplifies a difference between a first impedance on the first sense input end and a second impedance on the second sense input end to generate a sensing output signal. The data receiving circuit receives a plurality of bits of a data signal and provides the first impedance between the first sense input end and a reference grounding end according to the bits of the data signal. The reference circuit receives a plurality of bias voltages and provides the second impedance between the second sense input end and the reference grounding end according to the bias voltages.


