Analog Bitscan for NAND Memory Programming Control
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Solution Overview
Problem
Current programming techniques for non-volatile memory devices, such as NAND memory, face challenges in optimizing performance, reliability, and endurance due to limitations in verifying data states and adjusting programming parameters effectively.
Innovation Solution
The implementation of an analog bitscan operation that generates multiple output options (strong pass, weak pass, weak fail, and strong fail) to dynamically adjust programming parameters, such as verify voltage and programming voltage increments, based on the output of the bitscan operation, allowing for optimized programming and erasing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional binary bitscan operations are used for verifying memory cells, then the programming process is simple, but the precision of determining data state verification is insufficient
Solution Approach 1:
The patent transforms the static binary bitscan output into a dynamic multi-level output system. The analog bitscan operation produces multiple output options (first output option, second output option, third output option, fourth output option) based on the actual verification status, allowing the system to adaptively adjust programming parameters for different data state conditions.
Solution Approach 2:
The patent changes the parameter of bitscan operation from binary (pass/fail) to multi-level (four output options). This parameter change enables more granular control over programming verification, allowing differentiation between strongly passed, weakly passed, strongly failed, and weakly failed data states, thereby improving measurement precision.
2Reliability
If programming voltage is increased to ensure data state verification, then verification reliability improves, but over-programming occurs reducing memory endurance
Solution Approach 1:
The patent applies partial action by adjusting programming voltage based on actual verification needs rather than always applying maximum voltage. The analog bitscan results enable the system to apply only the necessary programming effort - using higher voltage only when needed (strong fail conditions) and lower voltage when verification is already sufficient (strong pass conditions), preventing unnecessary stress on memory cells.
Solution Approach 2:
The patent implements a feedback mechanism where the analog bitscan operation results directly influence subsequent programming voltage adjustments. The system continuously monitors verification status through multiple output options and adjusts programming parameters accordingly, creating a closed-loop control system that prevents over-programming while ensuring reliable verification.
3Manufacturing precision
If multiple verify operations are performed for each program loop, then programming accuracy improves, but programming time increases
Solution Approach 1:
The patent segments the verification process into distinct categories based on analog bitscan outcomes. Instead of uniformly performing multiple verify operations, the system divides verification into different paths: strong pass (minimal verification), weak pass (moderate verification), strong fail (extensive verification), and weak fail (adaptive verification), optimizing the verification depth for each case.
Solution Approach 2:
The patent dynamically adjusts the number and type of verify operations based on analog bitscan results. The verification strategy changes adaptively - performing fewer verifies when confidence is high (strong pass) and more verifies when confidence is low (strong fail), thereby balancing programming accuracy with time efficiency.
4Productivity
If programming parameters are fixed for all word lines, then device complexity is low, but programming performance across different word lines is suboptimal
Solution Approach 1:
The patent applies local quality by allowing different word lines to have different programming parameters based on their specific characteristics and analog bitscan results. Instead of a uniform programming approach, each word line can be programmed with optimized voltage levels and verify operations tailored to its local conditions, improving overall programming performance.
Solution Approach 2:
The patent enables parameter changes by dynamically adjusting programming voltage, verify voltage, and other parameters based on analog bitscan outcomes for each word line. This allows the system to optimize programming parameters locally for each word line rather than using fixed global parameters, enhancing programming efficiency and reliability.
Data Source
AI summary
The memory device includes a plurality of memory cells that are arranged in word lines, including a selected word line. Circuitry is configured to program at least some of the plurality of memory cells of the selected word line in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is further configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to control at least one programming parameter based on the output of the analog bitscan operation. The at least one programming parameter is an early program-verify termination parameter or a smart verify parameter.