Mixed-Signal IC Scan Chain Programming for Embedded Analog Blocks
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Solution Overview
Problem
Mixed-signal integrated circuits face challenges in reducing resource, IC area, and power consumption due to the need for extensive wiring between analog and digital units, which existing solutions like SPI or Parallel CPU I/F attempt to address but come with penalties in resources and power usage.
Innovation Solution
Implementing automatic scan chain insertion using Design-for-Test to program static bits in peripheral analog units, bypassing functional registers during programming and utilizing EDA tools for automation, which reduces the need for additional interfaces and resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual wiring is used to connect embedded digital blocks to analog unit interfaces, then configuration capability is achieved, but IC area and wiring complexity increase significantly
Solution Approach 1:
The patent merges the configuration interface functionality with the existing scan chain infrastructure used for testing. By integrating the configuration path into the scan chain, the patent eliminates the need for separate configuration wiring, thereby reducing IC area while maintaining full configuration capability for all digital block parameters.
Solution Approach 2:
The scan chain is designed to serve multiple functions: it performs both traditional testing operations and configuration operations. By making the scan chain universal, the patent eliminates the need for dedicated configuration interfaces, reducing wiring complexity and IC area while maintaining adaptability.
2Adaptability or versatility
If dedicated configuration interfaces like SPI or Parallel CPU I/F are added, then configuration capability is improved, but resource consumption and power usage increase
Solution Approach 1:
The patent combines the configuration function with the existing scan chain infrastructure, eliminating the need for separate dedicated configuration interfaces. This merging approach reduces resource consumption and power usage while maintaining full configuration capability through the shared scan chain pathway.
3Manufacturing precision
If extensive manual wiring is implemented for each configuration bit, then configuration precision is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges all configuration bit pathways into the single scan chain infrastructure. This approach maintains precise configuration capability for each bit while dramatically reducing wiring complexity, as the scan chain provides a systematic, automated pathway for reaching all configuration registers without extensive manual wiring.
Solution Approach 2:
The patent changes the operational parameters of the scan chain to enable configuration mode. By controlling the scan chain's operation state and data input, the system achieves precise configuration capability without the physical wiring complexity that would otherwise be required.
4Area of stationary object
If automatic scan chain insertion is used for configuration, then IC area and power are reduced, but programming speed decreases
Solution Approach 1:
The patent applies partial action by selectively using the scan chain for configuration only when needed, rather than continuously. Since configuration is typically a one-time or infrequent operation, the slower scan chain speed is acceptable and achieves the goal of reducing IC area and power consumption without significantly impacting overall system performance.
Data Source
AI summary
A mixed-signal integrated circuit includes an analog circuit comprising at least one digital block embedded in the analog circuit, the at least one digital block comprising a plurality of functional bits and a plurality of configuration bits, the plurality of functional bits providing for a functionality of the analog circuit according to a designed functionality and the plurality of configuration bits being usable for configuring a plurality of operational modes of the analog circuit; and a digital circuit comprising a scan chain configured to scan at least part of the functional bits of the digital block embedded in the analog circuit with respect to the designed functionality, wherein the scan chain is further configured to set at least part of the configuration bits of the digital block embedded in the analog circuit according to a selected operational mode of the plurality of operational modes of the analog circuit.