Analog Block Testing via Data Test Block and Eye Scan Controller
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Solution Overview
Problem
Analog blocks in system-on-chips (SoCs) are often decoupled from the programmable fabric, making them inaccessible for built-in self-test (BIST) systems, which limits their testing capabilities.
Innovation Solution
An apparatus and method that include a processing unit coupled to an input/output interface to control access to analog blocks, utilizing a data test block and a bit error rate tester to execute test patterns and determine bit error rates, and an eye scan controller to generate and adjust data eyes for analog blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If analog blocks are decoupled from the programmable fabric to improve their performance and integration in SoCs, then the system functionality is improved, but the testability of analog blocks deteriorates because they become inaccessible for BIST systems
Solution Approach 1:
A test interface is introduced as an intermediary component that bridges the gap between the digital test control logic and the analog blocks. This test interface includes analog-to-digital converters and test signal generators that enable digital test patterns to be applied to and measured from analog blocks, thereby making them testable without requiring direct fabric connectivity.
Solution Approach 2:
The testing system is segmented into distinct functional modules: a digital test controller, a test interface with analog-to-digital conversion capabilities, and the analog blocks under test. This segmentation allows each component to be optimized independently while maintaining overall system testability through standardized interfaces.
2Productivity
If traditional BIST systems are used to test analog blocks through fabric, then the testing can be performed, but the test precision and reliability are insufficient for accurate analog block characterization
Solution Approach 1:
The test system changes the parameters of test signals by providing controlled variations in amplitude, frequency, and timing through the test interface. This enables precise characterization of analog block performance across different operating conditions, significantly improving measurement precision compared to fixed fabric-based test patterns.
Solution Approach 2:
The patent replaces the mechanical/rigid fabric routing system with a flexible test interface that uses programmable signal generators and analyzers. This substitution allows for precise control and measurement of analog signals without the constraints of physical fabric connections, thereby improving test accuracy.
Data Source
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AI summary
An apparatus relating generally to a system-on-chip (200) is disclosed. In this apparatus, the system-on-chip (200) has at least one analog block (201), an input/output interface (221), a data test block (209), and a processing unit (230). The processing unit (230) is coupled to the input/output interface (221) to control access to the at least one analog block (201). The data test block (209) is coupled to the at least one analog block (201) through the input/output interface (221). The processing unit (230) is coupled to the data test block (209) and configured to execute test code having at least one test pattern. The data test block (209) under control of the test code executed by the processing unit (230) is configured to test the at least one analog block (201) with the test pattern.