Analog Buffer Voltage Holding Circuit for LCD Power Reduction
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Solution Overview
Problem
Existing analog buffers in liquid crystal display devices consume high power due to standby current from inverters, especially with increasing numbers of inverters, leading to significant power dissipation.
Innovation Solution
An analog buffer design utilizing a constant current source and a comparator to buffer input voltage to an output line, where the constant current source is turned off once the output voltage matches the input voltage, reducing unnecessary power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple inverters are used in the analog buffer, then the buffering capability is improved, but the power consumption increases due to standby current
Solution Approach 1:
The patent extracts the unnecessary standby current consumption by replacing the inverter-based buffering mechanism with a capacitor-based holding mechanism. The capacitor holds the voltage level without requiring continuous power supply, thereby removing the harmful standby current while maintaining the buffering function.
Solution Approach 2:
The patent changes the operational parameter from continuous power supply (inverter mode) to intermittent power supply (capacitor discharge mode). By controlling the power supply timing and using the capacitor's voltage holding capability, the system maintains buffering performance while dramatically reducing power consumption.
2Measurement precision
If more inverters are added to the analog buffer, then the voltage buffering performance is improved, but the power dissipation increases significantly
Solution Approach 1:
The patent removes the energy-dissipating inverter components and replaces them with a passive capacitor-based voltage holding circuit. This extraction of harmful energy-consuming elements while preserving the essential voltage buffering function directly addresses the contradiction between performance and power dissipation.
Solution Approach 2:
Instead of continuous power supply required by inverters, the patent uses periodic or controlled power supply to charge the capacitor, which then maintains the voltage level throughout the buffering period. This periodic charging approach maintains voltage performance while minimizing continuous power dissipation.
3Device complexity
If a simplified inverter-based buffer is used, then the circuit configuration is simpler, but the power consumption remains high due to standby current
Solution Approach 1:
The patent substitutes the active inverter-based electrical system with a passive capacitor-based voltage holding system. This replacement eliminates the need for continuous electrical power to maintain voltage levels, thereby reducing power consumption while keeping the circuit configuration relatively simple.
Data Source
AI summary
An analog buffer for buffering an input voltage to an output line is provided. The analog buffer includes a constant current source and a comparator. The constant current source supplies a constant current to the output line, and the comparator compares a voltage charged on the output line with the input voltage to turn-off the constant current source if it is determined that the voltage charged on the output line corresponding to the input voltage is buffered to the output line.