Error Detection in Analog CAMs Using Counter Sub-Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional content addressable memories (CAMs) are large, power-consuming, and expensive, and existing error detection techniques for analog CAMs (aCAMs) are inefficient, requiring significant computation resources and unable to effectively detect errors due to differences in functionality compared to other memory devices.
Innovation Solution
The implementation of new circuits with counter sub-circuits and redundancy aCAM cells that utilize modulo-2 counter sub-circuits and parity-check matrices to detect errors in aCAM arrays by applying specially-computed error-detection input vectors, reducing the number of reads required and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error detection techniques are used for aCAMs, then error detection capability is provided, but computation resources and time consumption increase significantly
Solution Approach 1:
The patent segments the aCAM array into multiple sub-arrays, with each sub-array having its own dedicated counter sub-circuit. This segmentation allows parallel error detection across multiple sub-arrays, reducing the overall computation time and resource requirements while maintaining comprehensive error detection capability.
Solution Approach 2:
The patent implements preliminary error detection by continuously monitoring match line outputs during normal aCAM operations. The counter sub-circuits accumulate match results in real-time, enabling error detection to occur concurrently with data processing rather than requiring separate detection passes, thus improving computational efficiency.
2Reliability
If conventional error detection techniques are used for aCAMs, then error detection capability is provided, but power consumption increases
Solution Approach 1:
The patent merges the error detection function with the existing aCAM match line evaluation logic. The counter sub-circuits utilize the same match line outputs that are already being processed for normal operations, eliminating the need for separate detection circuits and reducing overall power consumption while maintaining error detection capability.
Solution Approach 2:
The counter sub-circuits perform error detection using the inherent match line outputs from the aCAM array itself, without requiring external detection resources. The system essentially detects its own errors by monitoring its own operational outputs, reducing the need for additional power-consuming detection infrastructure.
3Reliability
If conventional error detection techniques are used for aCAMs, then error detection capability is provided, but the number of reads required increases
Solution Approach 1:
The patent implements continuous error detection by maintaining active counter sub-circuits that continuously accumulate match results during normal aCAM operations. This eliminates the need for periodic or separate detection reads, as error detection occurs continuously alongside data processing, significantly reducing the total number of reads required.
Data Source
AI summary
Examples of the presently disclosed technology provide new circuits for detecting errors in aCAMs with improved efficiency. Specifically designed around the structure and operation of aCAM arrays, these circuits include counter sub-circuits electrically connected to match lines of aCAM rows such that the counter sub-circuits receive match-related signals output from aCAM rows. The value stored by a counter sub-circuit may change in response to receiving a match signal, and may remain the same in response to receiving a mismatch signal. As will be described in greater detail below, the stored value of the counter sub-circuit may be used to detect/identify an error in its associated aCAM row after a set of (specially-computed) error-detection input vectors are sequentially applied to the circuit.