Analog Baud-Rate CDR Using Odd-Even Timing Error Extraction
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Solution Overview
Problem
Current clock and data recovery (CDR) methods, particularly at high data rates, face challenges with power consumption, area usage, and latency due to the need for complex digital implementations and oversampling, which are not feasible for modern CPU applications with hundreds of high-speed lanes.
Innovation Solution
An analog baud-rate Mueller-Muller algorithm-based CDR system utilizing track and hold circuits to create odd and even signals, which are then processed by comparators to derive a timing error signal, allowing for optimal sampling without oversampling and reducing the need for additional latency-inducing components like TX pre-cursor or RX FFE.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital Mueller-Muller algorithm is used for clock and data recovery, then timing extraction accuracy is improved, but power consumption and area usage increase
Solution Approach 1:
The patent replaces the digital Mueller-Muller algorithm implementation with an analog circuit implementation. The analog track and hold circuits continuously track the input signal and hold values for comparison, performing the timing extraction function in the analog domain rather than through digital sampling and computation. This substitution reduces power consumption and area while maintaining timing extraction accuracy.
Solution Approach 2:
The patent changes the operational parameters by using continuous analog tracking and holding at different phases (odd and even) rather than discrete digital sampling. The analog circuit operates at the baud rate without oversampling, changing the fundamental operating parameters from digital high-speed sampling to analog continuous tracking, which reduces the power and area requirements.
2Measurement precision
If digital Mueller-Muller algorithm with oversampling is used, then timing extraction capability is improved, but latency increases due to TX pre-cursor or RX FFE requirements
Solution Approach 1:
The patent replaces the digital signal processing approach requiring TX pre-cursor or RX FFE with an analog implementation that performs timing extraction directly at the baud rate. The analog track and hold circuits provide the necessary signal processing without requiring additional delay elements or pre-cursor operations, thereby reducing latency.
Solution Approach 2:
The patent extracts the timing information directly from the analog signal using track and hold circuits operated at the baud rate, removing the need for oversampling and the associated delay-inducing components. By taking out only the essential timing extraction function and implementing it in analog, the patent eliminates unnecessary latency.
3Use of energy by moving object
If baud rate CDR without oversampling is used, then power consumption is reduced, but timing information extraction becomes more difficult
Solution Approach 1:
The patent segments the timing extraction process into two parallel paths: odd track and hold circuits and even track and hold circuits. Each path operates at the baud rate and captures timing information at different phases. By segmenting the function and operating in parallel, the patent makes timing information extraction feasible at baud rate without oversampling, while maintaining low power consumption.
Solution Approach 2:
The patent introduces analog track and hold circuits as intermediary elements that capture and hold the input signal at different phases. These intermediaries make the timing information visible and measurable by providing stable, held values that can be compared to determine timing errors, solving the difficulty of extracting timing information without oversampling.
Data Source
AI summary
An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.