Analog Circuit Cell Array With Connected Gates And Shared Regions
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Solution Overview
Problem
The challenge is to produce analog circuits with a high level of integration and short lead time, while existing technologies face issues with manufacturing errors affecting transistor characteristics and the antenna effect, which degrades transistor matching and increases production time.
Innovation Solution
An analog circuit cell array is designed with a specific configuration of PMOS and NMOS basic cells, including common drain and source regions, connected gate electrodes, and strategically placed antenna diodes to minimize manufacturing errors and the antenna effect, allowing for high-accuracy transistor matching and efficient interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of basic cells are arranged in an array to increase integration level, then productivity is improved, but manufacturing precision deteriorates due to accumulated manufacturing errors affecting transistor characteristics
Solution Approach 1:
The patent divides each basic cell into multiple transistor units (first and second transistors) with shared regions (common source region, common drain region). This segmentation allows the cell to function as multiple transistors while reducing the number of discrete components needed, thereby increasing integration density without proportionally increasing manufacturing error accumulation.
Solution Approach 2:
The patent merges adjacent transistor structures by sharing source and drain regions between multiple transistors. Specifically, the first transistor and second transistor share a common source region and common drain region, reducing the total number of diffusion regions needed and improving manufacturing precision by reducing the number of discrete features that must be precisely fabricated.
2Power
If transistors are configured to perform the same operation to double driving capability, then power is improved, but device complexity increases due to additional interconnections
Solution Approach 1:
The patent combines multiple transistor functions into a single basic cell structure. The first transistor and second transistor share common source and drain regions, which eliminates the need for separate source and drain interconnections for each transistor. This merging approach doubles the driving capability while minimizing additional interconnection complexity.
Solution Approach 2:
The shared source region and shared drain region serve multiple functions: they act as source/drain for both the first transistor and second transistor simultaneously. This multi-functionality allows the basic cell to provide doubled driving capability without requiring separate dedicated interconnection structures for each transistor.
3Reliability
If manufacturing errors are present, then reliability deteriorates due to antenna effect degrading transistor matching, but lead time cannot be extended for adjustments
Solution Approach 1:
The patent incorporates antenna diodes in advance within the basic cell structure to protect against the antenna effect before it degrades transistor matching. These diodes are positioned to capture excess charge that would otherwise accumulate on metal interconnect lines during plasma processing, thereby cushioning the transistor structures from damage and maintaining matching accuracy without requiring post-manufacturing adjustments.
Solution Approach 2:
The antenna diode acts as an intermediary element between the metal interconnect lines and the transistor structures. It provides a safe path for charge dissipation, mediating the harmful antenna effect before it can reach and degrade the transistor matching characteristics.
Data Source
AI summary
An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.