Analog Circuit Analysis via Input Segmentation
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Solution Overview
Problem
Modern analog circuits controlled by a large number of digital inputs pose a challenge for comprehensive analysis due to the exponential growth of input combinations, making it impractical to exhaustively test all possible states, especially with current computationally expensive simulation techniques that result in prohibitively long runtimes.
Innovation Solution
A method and system that represent the circuit as a data structure with nodes and edges, identify boundary nodes, group digital inputs into mutually exclusive sets, and analyze all possible combinations of input states within each set, reducing the number of combinations needed to be tested through data structure traversal and grouping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exhaustive testing of all possible input combinations is performed, then complete circuit coverage is achieved, but testing time becomes prohibitively long
Solution Approach 1:
The patent segments the set of all digital inputs into multiple groups, where each group contains a subset of inputs. Instead of testing all inputs together (which would require 2^N combinations), the method tests each group separately for all possible combinations. This segmentation reduces the complexity from exponential in N to exponential in the size of each group, making the testing feasible while maintaining comprehensive coverage of each segment.
Solution Approach 2:
The patent applies partial action by testing only certain combinations of inputs rather than all possible combinations. By identifying and testing representative combinations within each input group, the method achieves sufficient circuit coverage without the prohibitive cost of exhaustive testing. This selective approach balances coverage requirements with practical time constraints.
2Adaptability or versatility
If the number of digital inputs increases, then circuit functionality is enhanced, but the number of input combinations to test grows exponentially
Solution Approach 1:
The patent divides the large set of digital inputs into multiple smaller groups. Each group is then analyzed separately, reducing the testing complexity from exponential in the total number of inputs to exponential in the size of each group. This segmentation allows modern circuits with many inputs to be tested feasibly while maintaining enhanced functionality.
Solution Approach 2:
The patent introduces a new dimension to the testing approach by organizing inputs into groups and systematically varying combinations within each group. This dimensional reorganization transforms the testing problem from a single large exponential space into multiple smaller exponential spaces, making the overall process manageable for circuits with many inputs.
3Measurement precision
If current simulation techniques are used, then circuit analysis is performed, but computational cost and runtime are prohibitively high
Solution Approach 1:
The patent segments the circuit analysis task by grouping digital inputs and analyzing the circuit behavior for each group separately. This segmentation reduces the computational burden by breaking down a single large-scale simulation into multiple smaller simulations, thereby reducing overall computational cost and energy consumption while maintaining analysis accuracy.
Solution Approach 2:
The patent applies partial action by performing circuit analysis on selected input combinations rather than all possible combinations. By identifying representative combinations within each input group and analyzing only those, the method achieves sufficient analysis accuracy with significantly reduced computational cost compared to exhaustive analysis.
Data Source
AI summary
A method for analyzing an analog circuit controlled by a plurality of digital inputs is presented. The circuit is represented with a data structure with nodes connected via edges, which represent a circuit component. The data structure can be traversed across all connected nodes; and said digital inputs can be toggled between two or more input states. The method steps include identifying a set of boundary nodes in the data structure which are at a digital-analog boundary of the data structure; for each digital input, identifying associated boundary nodes which are coupled with the digital input; grouping digital inputs into input sets, where each of the different input sets are associated with mutually exclusive sets of associated boundary nodes, and analyzing the circuit by successively analyzing one or more of the input sets for all possible combinations of inputs states within that set.