Parameterized Analog Circuit Modeling via Testbench Extraction
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Solution Overview
Problem
Current methods for simulating analog circuits, such as using SPICE and high-level languages like Verilog, are either extremely time-consuming or inaccurate, making them impractical for modeling and simulating analog circuits effectively, especially in analog design where circuit performance often deviates from ideal cases.
Innovation Solution
A method that generates a parameterized circuit model using a universal testbench approach to apply test simulations to a netlist definition, extracting performance parameters to populate a circuit model template, resulting in an abstracted representation that simulates circuit behavior with sufficient accuracy in a fraction of the time required for detailed netlist simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detailed netlist simulations are used to model analog circuits, then accuracy of circuit performance measurement is improved, but simulation time increases significantly
Solution Approach 1:
The patent performs preliminary test simulations on the detailed netlist model to extract accurate performance parameters before generating the abstracted model. This preliminary action captures essential circuit behaviors (voltage, current, power consumption) that are then embedded in the parameterized abstracted model, allowing subsequent simulations to use these pre-extracted parameters instead of running full detailed simulations again.
Solution Approach 2:
The patent creates an abstracted circuit model that copies only the essential performance characteristics from the detailed netlist model. By extracting key parameters through test simulations and embedding them in a simplified parameterized representation, the system creates a lightweight copy that maintains measurement accuracy for critical performance metrics while dramatically reducing simulation complexity and time.
2Productivity
If abstracted circuit models are used to reduce simulation time, then simulation speed is improved, but accuracy of circuit performance measurement deteriorates
Solution Approach 1:
The patent transforms the detailed netlist model into a parameterized abstracted model by extracting key performance parameters through test simulations. The abstracted model uses parameterized representations (such as voltage sources, current sources, and controlled sources with extracted parameters) that maintain accuracy for critical performance metrics while enabling faster simulation. This parameter transformation allows the model to operate at different abstraction levels with appropriate accuracy.
3Ease of operation
If high-level languages like Verilog are used to generate abstracted models, then ease of modeling is improved, but accuracy of circuit performance measurement deteriorates
Solution Approach 1:
The patent introduces an intermediary process that bridges the gap between high-level abstracted models and detailed netlist accuracy. Test simulations are performed as an intermediary step to extract accurate performance parameters from the detailed netlist, which are then embedded in the high-level parameterized model. This intermediary parameter extraction process allows the use of easy-to-manage high-level languages while maintaining measurement accuracy through data-driven parameterization.
4Reliability
If detailed netlist definitions are created to ensure accurate circuit modeling, then model accuracy is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the essential performance parameters from the detailed netlist model through targeted test simulations. By taking out only the critical parameters (voltage, current, power consumption, timing) needed for accurate performance measurement and embedding them in a simplified parameterized structure, the system reduces model complexity while maintaining reliability for critical performance assessments.
Data Source
AI summary
A method may include obtaining a netlist representation of a circuit comprising a single-cell (S-Cell) or multi-cell (M-Cell), performing one or more test simulations using the netlist representation of the circuit, receiving one or more parameters comprising performance metrics of the circuit responsive to the one or more test simulations, and generating a parameterized model of the circuit responsive to the one or more parameters.