Analog Computing Circuit Error Calibration for Fast MVM Accuracy
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Solution Overview
Problem
Neural network models require significant computational resources due to repeated matrix vector multiplication (MVM) operations, and existing techniques like pruning and quantization do not adequately address the need to reduce computation and data movement.
Innovation Solution
An analog computing circuit with resistive elements connecting rows and columns, incorporating error calibration through ADCs, where calibration signals are input to specific rows to adjust weight values and calibrate computation results, reducing the number of computations required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If analog computing circuit performs matrix vector multiplication computations, then computational speed is improved, but computation accuracy deteriorates due to errors in analog signal processing
Solution Approach 1:
The patent applies preliminary action by performing error calibration before the actual computation. Dedicated calibration rows receive calibration signals that pre-adjust the weight values of resistive elements, compensating for manufacturing variations and analog circuit errors before data computation begins. This preliminary calibration ensures that subsequent computations maintain high accuracy while preserving the speed advantages of analog processing.
Solution Approach 2:
The patent implements feedback mechanisms where computation results are monitored and used to adjust calibration parameters. The system measures actual computation outputs, compares them with expected values, and feeds back error information to modify calibration signals or weight values. This closed-loop feedback continuously corrects analog computation errors, maintaining accuracy without sacrificing computational speed.
2Measurement precision
If error calibration is performed using additional rows and ADCs, then computation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges calibration functions with computation functions by using the same crossbar array structure for both purposes. Calibration rows are integrated into the existing row-column architecture, and the same resistive elements serve both calibration and computation tasks at different time periods. This merging approach enables error calibration without requiring completely separate calibration hardware, thus improving accuracy while limiting the increase in device complexity.
Solution Approach 2:
The patent applies multi-functionality by designing the crossbar array to serve dual purposes: computation mode for matrix-vector multiplication and calibration mode for error correction. The same physical hardware (rows, columns, resistive elements) is reconfigured through signal control to perform different functions. This universal design allows the system to achieve high computation accuracy through calibration without proportionally increasing hardware complexity.
3Measurement precision
If more calibration rows are added to the analog computing circuit, then error calibration accuracy is improved, but the number of computations that can be performed simultaneously decreases
Solution Approach 1:
The patent implements periodic action by alternating between calibration operations and computation operations in time-multiplexed fashion. During dedicated calibration periods, calibration signals are applied to calibration rows to adjust weight values. During computation periods, the calibrated circuit performs matrix-vector multiplication. This periodic switching allows the system to achieve high calibration accuracy using dedicated calibration rows while maintaining high computational throughput by utilizing the full circuit capacity during computation phases.
Solution Approach 2:
The patent applies dynamics by making the circuit configuration flexible and reconfigurable through time-multiplexing. The same physical circuit can dynamically switch between calibration mode and computation mode. Calibration rows can be activated during calibration phases and deactivated or repurposed during computation phases. This dynamic reconfiguration allows the system to optimize for calibration accuracy when needed and for computational throughput when needed, resolving the contradiction between the two objectives.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit efficiently calibrates errors in computations, minimizing hardware size and computational load while maintaining accuracy, thereby optimizing resource utilization.
Implementation Method 1
The plurality of rows may be connected to the plurality of columns through resistive elements
Data Source
AI summary
An electronic device includes an analog computing circuit comprising a plurality of rows comprising a plurality of first rows to which a data signal for computations is input and one or more second rows to which a calibration signal for error calibration is input, and a plurality of columns connected to the plurality of rows and configured to output a computation result in which an error is calibrated, by accumulating signals transmitted from the connected plurality of rows in response to an input of the data signal and the calibration signal.