Analog Circuit Parameter Obfuscation via Transistor Biasing
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Solution Overview
Problem
Analog ICs face significant challenges in security due to their complex design and small footprint, making them vulnerable to intellectual property theft and counterfeiting, with existing protection techniques like watermarking and camouflaging being insufficient against untrusted foundries and end users who can reverse engineer and counterfeit IP.
Innovation Solution
A key-based obfuscation technique that masks critical biasing conditions of analog circuits, specifically targeting the phase locked loop (PLL) in a superheterodyne receiver, by varying transistor widths to obscure the target mixer frequency and other parameters, ensuring only the correct key sequence activates the proper biasing conditions, thereby protecting IP from counterfeiting and overproduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If watermarking and camouflaging techniques are used to protect analog IP, then some level of protection is provided, but the foundry and end users can still reverse engineer and counterfeit the IP
Solution Approach 1:
The patent applies parameter changes by modifying transistor width parameters to create multiple possible biasing conditions. The analog circuit is designed with variable transistor widths that can be configured in different combinations, each producing different functional parameters. This allows the same physical circuit to exhibit multiple possible behaviors, making reverse engineering difficult because the observed parameters do not uniquely identify the original design intent.
2Ease of manufacture
If the foundry is given access to all production information, then manufacturing is enabled, but reverse engineering and counterfeiting become possible
Solution Approach 1:
The patent implements preliminary action by pre-configuring the analog circuit with multiple possible biasing conditions during the design phase. Transistor widths are deliberately designed to allow different configuration combinations before the circuit is manufactured. This preliminary structuring ensures that even when the foundry receives the full design information, they cannot determine which configuration represents the intended functionality, as multiple configurations are physically possible.
3Reliability
If transistor widths are varied to obscure target mixer frequency, then security is improved, but active transistor area increases by 6.3%
Solution Approach 1:
The patent applies segmentation by dividing the analog circuit into multiple functional blocks, each with its own set of variable transistor widths. Instead of obfuscating the entire circuit with a single large configuration space, the circuit is segmented into smaller independent sections that can be configured separately. This segmentation achieves security through cumulative effect across multiple segments while keeping the area overhead of each individual segment manageable.
4Loss of information
If multiple biasing conditions are created, then the desired functional parameters are masked, but the circuit requires precise biasing control
Solution Approach 1:
The patent introduces an intermediary configuration layer between the physical circuit and the functional output. The variable transistor widths act as intermediaries that map physical dimensions to multiple possible functional parameters. This intermediary structure allows the physical circuit to remain precise and manufacturable, while the configuration space provides the masking effect. The intermediaries (transistor width combinations) absorb the complexity, allowing precise manufacturing of each individual transistor while achieving parameter masking at the system level.
Data Source
AI summary
A key based technique that targets obfuscation of critical circuit parameters of an analog circuit block by masking physical characteristics of a transistor (width and length) and the circuit parameters reliant upon these physical characteristics (i.e. circuit biasing conditions, phase noise profile, bandwidth, gain, noise figure, operating frequency, etc.). The proposed key based obfuscation technique targets the physical dimensions of the transistors used to set the optimal biasing conditions. The widths and/or lengths of a transistor are obfuscated and, based on an applied key sequence, provides a range of potential biasing points. Only when the correct key sequence is applied and certain transistor(s) are active, are the correct biasing conditions at the target node set.