Analog Circuit Transistor Sizing via Block Segmentation
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Solution Overview
Problem
Current methods for designing analog IP blocks in systems-on-chips (SoCs) are inefficient due to the lack of a general method for providing behavioral descriptions, leading to lengthy synthesis times and potential optimizer drawbacks in both simulation-based and knowledge-based optimization categories.
Innovation Solution
A method that breaks down the analog circuit into blocks, defines electrical constraints and parameters, selects operators for calculating parameter values, generates structured graphs, identifies conflicts, and resolves them to automatically calculate transistor dimensions and bias points, allowing for faster design and simulation of analog IP blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation-based optimization is used, then complex standard models can be utilized, but synthesis time increases substantially (several hours)
Solution Approach 1:
The circuit is broken down into a set of blocks, each with defined functionality and specific transistor arrangements. This segmentation allows the complex circuit to be analyzed in manageable parts, reducing overall synthesis time while maintaining model accuracy through systematic block-level processing
Solution Approach 2:
The method changes the approach from simulation-based parameter verification to equation-based parameter calculation. By using mathematical models and equations to directly compute transistor dimensions and bias points, the synthesis time is dramatically reduced while maintaining reliability through rigorous mathematical relationships
2Loss of time
If knowledge-based optimization is used, then synthesis time becomes very fast, but modeling by equations is time-consuming and complex
Solution Approach 1:
The complex modeling task is segmented into block-level models with standardized representations. Each block has defined electrical parameters and relationships, reducing the overall modeling complexity while enabling fast synthesis through systematic assembly of block models
Solution Approach 2:
The method creates universal block models that can represent multiple circuit functionalities through standardized parameter definitions. These reusable block models reduce modeling complexity by providing templates that can be applied across different circuit designs, enabling fast synthesis without repeated complex derivations
3Extent of automation
If optimizer is used, then automated parameter calculation is achieved, but solutions may have drawbacks in terms of design control and conflict management
Solution Approach 1:
The method applies partial automation by automatically calculating transistor parameters while maintaining designer control over block-level specifications and constraints. This partial automation approach achieves efficient parameter calculation without completely removing designer oversight, allowing easy detection and resolution of design conflicts
Solution Approach 2:
The systematic block modeling approach provides feedback mechanisms where block parameters and constraints can be verified for consistency. This enables automated calculation while maintaining design control through verification steps that detect conflicts and allow designer intervention when needed
Data Source
AI summary
A method for determining electrical parameter values of the transistors of an analog circuit of a system on chip includes breaking the circuit down into a set of blocks connected to one another; establishing the wiring diagram of said circuit; defining a set of electrical constraints that are specific to said circuit, blocks and transistors of each block; defining electrical parameters of the circuit, block and transistors; selecting for each transistor of the circuit an operator for calculating the electrical parameter values of said transistor; generating structured diagrams of each block of the circuit from the defined constraints and the chosen operators; assembling said structured diagrams of blocks into a general diagram of the circuit; identifying whether there is any conflict; and, if so, emitting an alarm signal.