Analog Clock Divider Using Ramp Detection for Wide Ratio Range
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Solution Overview
Problem
Divider circuits in integrated circuits face challenges in maintaining high resolution while providing a large division factor range, often consuming excessive space and power, especially when dealing with high frequency clock signals.
Innovation Solution
The implementation of a divider circuit that includes a ramp generator, synchronous detector, and control circuit, utilizing a capacitance and current source to generate and control a ramp signal, allowing for adjustable division factors and reduced power consumption through a combination of synchronous logic and voltage threshold detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If synchronous logic circuits (flip-flops) are used to divide high frequency clock signals, then division factor range is improved, but power consumption increases
Solution Approach 1:
The patent replaces traditional synchronous logic circuits (flip-flops) with an analog-based divider circuit that uses a ramp generator and synchronous detector. This substitution eliminates the need for multiple sequential flip-flop stages, significantly reducing power consumption while maintaining the ability to achieve large division factors through the analog ramp mechanism.
Solution Approach 2:
The invention changes the operating parameters by using an analog ramp voltage that increases linearly over time, detected against a threshold voltage. This analog parameter-based approach allows for large division factors without requiring cascaded logic stages, thereby reducing power consumption while maintaining adaptability across different division ratios.
2Adaptability or versatility
If synchronous logic circuits are used for clock division, then division capability is improved, but circuit area increases
Solution Approach 1:
The patent substitutes the mechanical/logic-based flip-flop chain with an analog circuit comprising a ramp generator, comparator, and synchronous detector. This analog implementation achieves the same division capability with significantly fewer components and smaller circuit area, as it avoids the need for multiple sequential logic stages.
Solution Approach 2:
The analog divider circuit serves multiple functions within a compact structure: the ramp generator creates the time-base signal, the comparator detects threshold crossings, and the synchronous detector synchronizes output with the clock. This multi-functional integration reduces overall circuit area while maintaining full division capability.
3Speed
If high frequency input clock is divided down, then output frequency range is improved, but resolution decreases
Solution Approach 1:
The patent uses an analog ramp generator that creates a continuous, linearly increasing voltage signal rather than discrete logic transitions. This continuous analog representation maintains precision information throughout the division process, allowing high-resolution output even when dividing high-frequency inputs, as the ramp's slope and threshold detection preserve fine timing details.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient generation of variable frequency clock signals with high resolution and a wide division factor range, reducing power dissipation and circuit complexity, making it suitable for various computing and telecommunications applications.
Implementation Method 1
a current source circuit configured to supply a charging current to a capacitance
Implementation Method 2
a voltage threshold detector circuit configured to receive the ramp signal and to generate a detection signal responsive thereto
Data Source
AI summary
A divider for use in an integrated circuit chip, such as a clock generator chip, includes a ramp generator circuit configured to generate a ramp signal and a synchronous detector circuit configured to receive the ramp signal and an input clock signal and to responsively control the ramp signal generator circuit to generate an output clock signal at an output of the synchronous detector circuit. In some embodiments, the synchronous detector circuit may include a voltage threshold detector circuit configured to receive the ramp signal and to generate a detection signal responsive thereto and a synchronous latch circuit having a clock input configured to receive the input clock signal and a data input configured to receive the detection signal. The synchronous latch circuit may be configured to control the ramp generator circuit.