High-Speed Analog Comparator With Low Slewing Latency
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Solution Overview
Problem
Conventional asynchronous analog comparators are too slow for high-speed analog applications due to slewing latency and have high impedance nodes that limit bandwidth, making them unsuitable for high-frequency signal processing.
Innovation Solution
An asynchronous analog comparator design featuring two voltage-to-current-to-voltage converters with reversed differential inputs and a bias feedback loop, which includes transconductors and transimpedance amplifier loads, to achieve low slewing latency and optimal biasing, allowing for efficient high-speed signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional asynchronous analog comparator is used, then the circuit can be implemented with simple structure, but the response speed is too slow due to slewing latency
Solution Approach 1:
The comparator is divided into two separate voltage-to-current-to-voltage converter circuits operating in parallel, each handling one polarity of the differential input. This segmentation allows simultaneous processing of positive and negative differential signals, eliminating the sequential operation that causes slewing latency in conventional comparators.
Solution Approach 2:
The bias current is made dynamically adjustable through a feedback loop that monitors the output voltages and automatically balances the bias currents between the two converters. This dynamic adaptation optimizes the response speed by ensuring both converters operate at peak performance regardless of input signal conditions.
2Productivity
If high impedance nodes are used in the comparator, then the circuit can operate with lower power consumption, but the bandwidth is limited
Solution Approach 1:
A feedback loop continuously monitors the output voltages of the two converters and adjusts the bias currents accordingly. This feedback mechanism maintains optimal operating conditions for high bandwidth operation without requiring continuously high power consumption, as the bias currents are adjusted dynamically rather than maintained at maximum levels.
Solution Approach 2:
The bias current parameters are changed dynamically based on operating conditions. The feedback loop adjusts the bias current magnitude to match the signal amplitude and frequency requirements, allowing the circuit to achieve high bandwidth when needed while consuming less power during low-bandwidth operations.
3Loss of time
If two voltage-to-current-to-voltage converters with reversed differential inputs are used, then slewing latency is reduced, but the device complexity increases
Solution Approach 1:
The two converters are configured with reversed differential inputs, creating an asymmetric arrangement where one converter handles positive differential signals while the other handles negative differential signals. This asymmetric configuration allows both converters to operate simultaneously without interference, eliminating the slewing latency that would occur in a symmetric sequential design.
Solution Approach 2:
The two separate converter circuits are merged into a single integrated comparator structure with shared biasing and feedback mechanisms. This merging reduces the overall device complexity by consolidating common functions while maintaining the parallel processing capability that reduces slewing latency.
Data Source
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AI summary
An apparatus relating generally to voltage conversion includes an amplifier (101) coupled to receive an input voltage (121) and a reference voltage (122). First and second converters (111, 112) are coupled to the amplifier (101) to receive a bias voltage (102). The first converter (111) includes a first transconductor (131) coupled to receive the bias voltage (102) to adjust a first tail current, and a first differential input (117P, 117M). A first inverter (141) of the first converter (111) has a first feedback device (145) coupled input-to-output to provide a first transimpedance amplifier load. The first inverter (141 ) is coupled to the first transconductor (131). The second converter (112) includes a second transconductor (132) coupled to receive the bias voltage (102) to adjust a second tail current, and a second differential input (117M, 117P). A second inverter (142) of the second converter (112) has a second feedback device (145) coupled input-to-output to provide a second transimpedance amplifier load. The second inverter (142) is coupled to the second transconductor (132).