Analog Computation Circuit for Vector-Matrix Multiplication

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Solution Overview

Problem

Current computation circuits are inefficient in performing vector-matrix multiplication operations, which are crucial for neural network operations in artificial intelligence applications such as image recognition and autonomous vehicles.

Innovation Solution

A computation circuit comprising a computing cell array, a vector input circuit, a matrix control circuit, and a vector output circuit, which generates output voltages corresponding to the dot product of an input vector and a matrix, utilizing a semiconductor device with a command decoder, data IO buffer, and computation circuit to perform efficient vector-matrix multiplication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional computation circuits are used for neural network operations, then general-purpose computing is achieved, but computational efficiency for vector-matrix multiplication is insufficient

Engineering Contradiction:

Improvecomputational efficiencyVSAvoidcircuit structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The computation circuit is segmented into multiple computing cells arranged in an array structure, where each computing cell independently performs multiplication of a weight value and an input value. This segmentation enables parallel processing of multiple elements in vector-matrix multiplication operations, significantly improving computational efficiency for neural network workloads while maintaining manageable complexity through modular design

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The computing cells are designed with universal functionality to perform both weight storage and multiplication operations. Each computing cell can store weight values in capacitors and perform analog multiplication by applying input voltages, allowing the same hardware structure to handle various neural network operations including forward propagation, backward propagation, and different types of matrix multiplications

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Power

If more computing resources are allocated for AI applications, then computational capability is improved, but power consumption increases

Engineering Contradiction:

Improvecomputational capabilityVSAvoidpower consumption

Core Design Contradiction:

PowerVSUse of energy by moving object

Solution Approach 1:

The circuit replaces digital binary switching operations with analog continuous voltage operations. Weight values and input values are represented as continuous voltage levels rather than discrete binary states, enabling multiplication through analog circuit operations that consume less power than equivalent digital computations, thereby improving computational capability while reducing power consumption

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The design merges weight storage and computation functions into the same computing cell structure. Weight values are stored in capacitors within each computing cell and simultaneously used for multiplication operations, eliminating the need for separate memory and computation units. This merging reduces data transfer overhead and associated power consumption while improving overall computational efficiency

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution enables efficient performance of vector-matrix multiplication operations, enhancing the computational efficiency for neural networks and supporting advanced AI applications like image recognition and autonomous vehicles.

Implementation Method 1

a computing cell array configured to provide a plurality of physical values respectively corresponding to a plurality of elements of a matrix; wherein the computing cell array includes a plurality of computing cells respectively corresponding to a plurality of elements of the matrix, and each of the computing cells includes an effective capacitance

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

a vector input circuit configured to provide a plurality of input voltages corresponding to an input vector to the computing cell array

Methodology Applied

Scientific EffectVoltage: Electric Field

Implementation Method 3

a vector output circuit configured to output a plurality of output voltages each corresponding to a dot product between the input vector and a column vector of the matrix according to the plurality of input voltages and the plurality of effective capacitances

Methodology Applied

Scientific EffectElectrical charge storage and multiplication: Capacitance

Data Source

PatentUS11455371B2Computation circuit for performing vector-matrix multiplication and semiconductor device including the computation circuit

Publication Date: 2022.09.27 SK HYNIX INC

AI summary

A computation circuit includes a computing cell array configured to provide a plurality of physical values respectively corresponding to a plurality of elements of a matrix; a vector input circuit configured to provide a plurality of input voltages corresponding to an input vector to the computing cell array; and a vector output circuit configured to output a plurality of output voltages each corresponding to a dot product between the input vector and a column vector of the matrix according to the plurality of input voltages and the plurality of effective capacitances.