Analog Computing Circuit Data Scaling for Neural Network Precision
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Solution Overview
Problem
Current machine learning models, particularly neural network models, face inefficiencies in computational operations due to the need for numerous matrix vector multiplication (MVM) operations, which consume significant time, processing power, and energy resources, and are prone to errors from quantization and noise in crossbar array structures with resistive elements.
Innovation Solution
An electronic device with an analog computing circuit that scales inputs and weights using specific scaling factors to operate outside preset ranges, reducing noise and errors by rescaling outputs, thereby enhancing operational precision and reducing the impact of quantization and noise in MVM operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If quantization is applied to reduce computational complexity, then processing speed improves, but measurement precision deteriorates
Solution Approach 1:
The patent changes the precision parameter of computational operations dynamically. It performs high-precision operations for critical calculations (such as weight updates and gradient computations) while using low-precision operations for less critical tasks (such as activation functions and data loading). This selective precision approach maintains overall model accuracy while significantly reducing computational overhead and energy consumption.
Solution Approach 2:
The patent introduces dynamic precision adjustment mechanisms that adapt the precision level based on the computational context, model layer, and operational phase. During training, different precision levels are applied to different layers and operations, and during inference, the system dynamically selects precision levels based on input data characteristics and required output accuracy.
2Use of energy by moving object
If data movement is minimized to improve efficiency, then energy consumption reduces, but device complexity increases
Solution Approach 1:
The patent segments the computational system into distinct functional units with specialized precision requirements: high-precision units for weight storage and gradient computation, low-precision units for activation functions and data processing, and mixed-precision units for matrix operations. This segmentation allows each unit to operate at optimal precision levels, reducing overall data movement and energy consumption while maintaining computational accuracy.
Solution Approach 2:
The patent introduces precision conversion intermediaries that facilitate data transfer between high-precision and low-precision units. These intermediaries perform necessary precision transformations and validations, enabling efficient data movement across precision boundaries without requiring full-precision data to be transmitted throughout the entire system.
3Productivity
If low-precision operations are used to reduce computational load, then processing speed improves, but reliability deteriorates
Solution Approach 1:
The patent applies different precision qualities to different parts of the computational process based on their specific requirements. Critical components such as weight parameters and gradient calculations use high precision (16-bit or 32-bit), while less sensitive operations such as activation functions and batch normalization use low precision (8-bit or lower). This local quality differentiation maintains computational reliability where needed while maximizing throughput where possible.
Solution Approach 2:
The patent implements feedback mechanisms that monitor the impact of low-precision operations on model performance and adjust precision levels accordingly. During training, the system tracks accuracy degradation from low-precision operations and dynamically adjusts precision levels or applies correction factors to maintain model convergence and final accuracy.
Data Source
AI summary
An electronic device and method with data scaling is provided herein. The electronic device may include a computing device that includes an analog computing circuit, where the computing device may scale an input of the analog computing circuit using a first scaling factor and/or scale a weight of the analog computing circuit using a second scaling factor, where the input includes a plurality of input values within a preset input maximum range of values of the computing device, and the weight includes a plurality of weight values within a preset weight maximum range of values of the computing device, and rescale an output of the analog computing circuit based on the first scaling factor and/or the second scaling factor. The first and second scaling factors may respectively scale values of the input and the weight to exceed respective preset maximum ranges of values.