Analog Computing Unit With Shared Bit Lines for Negative Weights
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Solution Overview
Problem
Existing analog computing units require separate ADCs for positive and negative weights, leading to increased size and power consumption due to the need for multiple bit lines and ADCs, which are area and energy-intensive.
Innovation Solution
Analog computing unit with a split-gate NOR flash memory cell array where positive and negative weights are stored in alternating memory cells connected in series, sharing a common bit line, allowing current cancellation and reducing the need for half the number of ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate ADCs are used for positive and negative weights, then measurement precision is improved, but device complexity and area increase
Solution Approach 1:
The patent merges the functionality of separate ADCs for positive and negative weights into a shared ADC resource. By alternating memory cells (even columns for positive weights, odd columns for negative weights) and using current cancellation techniques, a single ADC can service multiple bit lines that previously required dedicated ADCs, thereby reducing device complexity while maintaining measurement precision through differential signaling
Solution Approach 2:
The ADC is designed to serve multiple functions by handling both positive and negative weight computations through a unified architecture. The same ADC infrastructure processes signals from both even and odd column groups, making the ADC system universal rather than specialized for single-purpose weight types, thus reducing the total number of ADCs required
2Measurement precision
If separate ADCs are used for positive and negative weights, then measurement precision is improved, but power consumption increases
Solution Approach 1:
By merging ADC resources to serve both positive and negative weight bit lines through alternating column groups, the patent reduces the total number of ADCs operating simultaneously. This consolidation directly reduces power consumption while maintaining precision through the shared ADC infrastructure that handles both weight types sequentially or through multiplexing
3Measurement precision
If more bit lines are used for separate positive and negative weights, then measurement precision is improved, but area increases
Solution Approach 1:
The patent introduces column-based differentiation (even columns for positive weights, odd columns for negative weights) as a new organizational dimension. This vertical/categorical separation allows weight differentiation without requiring additional horizontal space for separate bit line groups, effectively using the column index dimension to encode weight polarity information and reduce area
Data Source
AI summary
An object is to provide a new analog computing unit capable of reducing the size of an analog computing unit and reducing the amount of power consumption by reducing use of analog-to-digital converters (ADCs) to half as compared to prior arts. In a flash memory cell array included on the analog computing unit according to one embodiment, unlike the prior arts, two memory cells are not disposed in a symmetric structure, but memory cells in one bit line are arranged in a series type in which the memory cells for storing positive weights and the memory cells for storing negative weights alternate one by one. Namely, the memory cells has the structure in which a source of one of two memory cells and a drain of the other are shared through one bit line.