Analog Current Memory Droop Compensation Circuit
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Solution Overview
Problem
Conventional neural networks face high latency and energy consumption due to off-chip DRAM access, and current analog memory solutions like memristors suffer from variability and compatibility issues with standard CMOS technologies, leading to accuracy and practical challenges.
Innovation Solution
An analog current memory circuit with a ramp current generator, storage transistor, write-enable transistor, charge pump transistor, comparator, and controller, which operates in a write phase and compensation phase to maintain accurate current storage by compensating for droop caused by subthreshold leakage, using a small and low-power droop compensation circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If off-chip DRAM is used for data storage, then large storage capacity is achieved, but access latency and energy consumption increase significantly
Solution Approach 1:
The memory system is segmented into off-chip DRAM for bulk storage and on-chip SRAM for frequently accessed data, with each segment serving different purposes. The SRAM cache holds weights and feature maps that need rapid access, while DRAM provides large-capacity storage, resolving the contradiction between storage capacity and access speed through spatial segmentation of the memory hierarchy.
2Speed
If on-chip SRAM is used for local data storage, then access speed and energy efficiency improve, but memory density is limited due to transistor requirements
Solution Approach 1:
The patent replaces conventional digital SRAM cells with analog memory elements (memristors or floating gate transistors) that can store multiple bits per cell through variable conductance or threshold voltage. This substitution enables higher memory density on-chip while maintaining fast access speeds, as analog cells require fewer transistors per stored bit compared to digital SRAM.
3Quantity of substance
If memristors are used for analog memory storage, then multibit storage capacity and parallel computation capability are achieved, but variability and compatibility with standard CMOS technologies become issues
Solution Approach 1:
The patent implements feedback mechanisms including read-disturb compensation circuits and variability compensation circuits that continuously monitor and adjust the analog memory values. During read operations, the feedback circuit detects changes in conductance caused by read disturbances and compensates for them. Similarly, variability compensation circuits measure process variations and adjust reference voltages or currents to maintain computational accuracy, thereby improving reliability while preserving high storage capacity.
4Productivity
If memristors are used for analog memory, then parallel MAC operations are enabled, but endurance and high-voltage requirements present practical challenges
Solution Approach 1:
The patent employs periodic refresh operations to maintain analog memory values over time. A refresh circuit periodically reads and rewrites the stored values to counteract drift and degradation effects, effectively extending the operational duration and endurance of the analog memory. This periodic maintenance allows the system to sustain high-throughput parallel MAC operations for extended periods without significant accuracy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively maintains accurate current storage over time with minimal power consumption and area requirements, reducing errors and improving the reliability of analog neural networks by compensating for droop in the stored current.
Implementation Method 1
a ramp current generator producing a ramp current
Implementation Method 2
a comparator electrically coupled to the storage transistor and the ramp current generator
Implementation Method 3
the controller produces a charge pump signal to turn on the charge pump transistor to increase the stored current by a predetermined increment
Implementation Method 4
CP is a parasitic capacitance at the gate node of M1
Data Source
AI summary
An analog current memory circuit includes a ramp current generator producing a ramp current; a storage transistor, a write-enable transistor, a charge pump transistor, a clock generator producing a clock signal having a first state and a second state, a comparator electrically coupled to the storage transistor and the ramp current generator, a controller electrically coupled to the comparator and the clock generator, and a switch electrically coupled to the controller and the ramp current generator. During the write phase, the controller produces a write-enable signal to turn on the write-enable transistor to produce a stored current in the storage transistor, the stored current being substantially equal to an input current to the analog current memory circuit. During the compensation phase, the switch electrically couples the ramp current generator and the storage transistor to the comparator.