Analog Data Path Bypasses Digital Core in Multiplexers
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Solution Overview
Problem
Current telecom and datacom multiplexers and demultiplexers face inefficiencies due to high power consumption and latency caused by standard digital core designs, which are non-optimized and require significant data rate dropping, leading to large layout areas and high parasitics.
Innovation Solution
The implementation of an analog domain data path that bypasses the digital core data path, allowing for reduced power consumption and latency by using low power static CMOS and asynchronous design techniques, with a digital core maintained for necessary functions and powered down when not in use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard digital core data path is used for multiplexing and demultiplexing, then data processing functionality is achieved, but power consumption increases and latency increases
Solution Approach 1:
The patent segments the data path into two separate domains: an analog domain data path for high-speed multiplexing/demultiplexing operations and a digital core data path for diagnostic and calibration functions. This segmentation allows each domain to be optimized for its specific function, with the analog path handling time-critical data transmission and the digital core handling non-time-critical maintenance tasks, thereby reducing overall power consumption while maintaining functionality.
Solution Approach 2:
The patent extracts the multiplexing and demultiplexing functions from the standard digital core and implements them in the analog domain using custom schematic-based design. This extraction removes the power-consuming digital multiplexing/demultiplexing stages while preserving the essential data routing functionality, directly addressing the power consumption issue.
2Ease of operation
If data rate is dropped to pass through standard digital core, then data can be processed by digital logic, but latency increases and additional power is consumed
Solution Approach 1:
The patent substitutes the mechanical/digital data rate dropping process with an analog domain implementation that maintains high data rates throughout the multiplexing/demultiplexing stages. By using analog circuits operating at the full data rate instead of digitally dropping and reconstructing the data rate, the system eliminates the time-consuming digital processing stages while preserving digital processing capability where needed.
3Ease of manufacture
If standard place and route digital core is used, then design is achieved using standard processes, but layout area increases and parasitics increase
Solution Approach 1:
The patent applies local quality by using custom schematic-based analog design specifically for the multiplexing/demultiplexing data path where high performance is critical, while still using standard digital core for auxiliary functions. This localized custom design approach optimizes the critical path for speed and area efficiency without requiring the entire design to be custom, balancing manufacturability with performance.
4Ease of manufacture
If standard place and route digital core is used, then design is achieved using standard processes, but parasitics increase
Solution Approach 1:
By segmenting the data path into analog and digital domains, the patent isolates the high-speed analog multiplexing/demultiplexing operations from the digital core. This segmentation prevents the digital switching activity and associated parasitics from contaminating the sensitive analog signal paths, reducing overall parasitic effects while maintaining standard manufacturing processes for the digital portions.
Data Source
AI summary
Described herein are systems and methods for reducing power consumption, latency, and chip complexity in a datacom/telecom multiplexer and demultiplexer. Adding a high frequency analog domain data path around or in place of a standard digital core data path allows the elimination of the demultiplexing and multiplexing stages required to drop the data rate of data streams down to that required for a standard digital core. Latency is also reduced due to the higher operating frequency of sequential elements required for data operations. The digital core can be powered down when not in use, and can be activated when necessary.