Analog Defect Simulation via Netlist Node Injection
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Solution Overview
Problem
Current methods for digital fault simulation and testing in integrated circuits are inadequate for accurately and efficiently assessing defects in analog circuits, which account for a significant portion of field returns in mixed signal ICs, necessitating improved analog fault simulation capabilities.
Innovation Solution
A method and system for simulating defects in analog circuits by defining and injecting defect models into a netlist, allowing for the identification and simulation of short and open faults at specific nodes, enabling comprehensive defect analysis and improving test coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If digital fault simulation methods are used for analog circuits, then the testing process is simplified, but the accuracy of defect detection is insufficient
Solution Approach 1:
The patent segments the defect simulation process into distinct components: defect model definition, scope specification, netlist compilation, node identification, defect injection, and simulation execution. This segmentation allows digital simulation methods to be systematically applied to analog circuits while maintaining accuracy through specialized defect models for analog components.
2Reliability
If comprehensive defect models are defined for all circuit nodes, then defect detection coverage is improved, but computational complexity increases
Solution Approach 1:
The patent applies local quality by defining defect scopes that selectively apply defect models to specific circuit regions or components rather than uniformly to all nodes. This allows comprehensive defect detection in critical analog blocks while reducing computational complexity in less critical areas, optimizing the balance between coverage and resource usage.
3Measurement precision
If analog fault simulation capability is enhanced, then defect detection accuracy is improved, but simulation time increases
Solution Approach 1:
The patent performs preliminary actions by pre-defining defect models and scopes, and pre-identifying candidate nodes before actual defect injection and simulation. This preparation work is done once and reused across multiple simulation runs, reducing the time required for repeated analog fault simulations while maintaining high detection accuracy.
Data Source
AI summary
A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied, injecting the multitude of defects at the identified nodes, and simulating the analog circuit design using the injected defects.