Transistor-Level Defect Coverage in Analog IC Sub-Circuits
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Solution Overview
Problem
Current methods for defect coverage and fault simulation in integrated circuits, particularly in analog circuits, are inefficient due to high computational resource and processing time requirements, leading to unsatisfactory fault coverage and increased manufacturing costs.
Innovation Solution
The method involves partitioning the analog circuit of a mixed-signal IC design into sub-circuits and identifying fault-sensitive internal nets based on these sub-circuits, using channel-connected graphs and algorithms to reduce the number of simulations needed for high test coverage, thereby improving defect and fault simulation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault simulation is performed on the entire analog circuit, then fault coverage is improved, but computational resource consumption and processing time increase significantly
Solution Approach 1:
The patent partitions the analog circuit into multiple sub-circuits based on connectivity analysis. By dividing the large-scale circuit into smaller independent sub-circuits, the simulation can be performed on each sub-circuit separately, reducing the computational complexity from O(n²) to O(k²) where k is the size of sub-circuits. This segmentation maintains fault coverage while significantly improving simulation efficiency.
Solution Approach 2:
The patent extracts and identifies critical sub-circuits that contain the majority of fault-sensitive internal nets. By focusing simulation efforts on these extracted sub-circuits rather than the entire circuit, the method achieves high fault coverage with reduced computational resources. The extraction process identifies sub-circuits with the highest fault sensitivity metrics.
2Productivity
If the number of simulations is reduced to save computational resources, then processing time decreases, but fault coverage becomes insufficient
Solution Approach 1:
The patent applies local quality by assigning different simulation priorities to different sub-circuits based on their fault sensitivity. Sub-circuits with higher fault sensitivity receive more comprehensive simulation coverage, while less critical sub-circuits use reduced simulation sets. This localized approach ensures adequate fault coverage is maintained in critical areas while reducing overall computational burden.
Solution Approach 2:
The patent performs partial simulation by selecting a representative subset of test patterns for each sub-circuit rather than exhaustively testing all patterns. The method uses fault sensitivity analysis to identify the most critical test patterns, applying partial action that achieves sufficient fault coverage without the computational cost of complete exhaustive testing.
3Reliability
If traditional fault simulation methods are used on mixed-signal ICs, then both digital and analog fault coverages are determined, but the majority of failures in analog circuits are not adequately detected due to resource constraints
Solution Approach 1:
The patent segments the mixed-signal IC into digital and analog sub-circuits, with further segmentation of analog circuits into fault-sensitive sub-circuits. This hierarchical segmentation allows focused simulation resources to be applied to analog portions that are most prone to failures, improving analog fault detection capability while managing computational complexity through structured division.
Solution Approach 2:
The patent changes the simulation parameters by dynamically adjusting the number of test patterns and simulation depth based on sub-circuit characteristics. For analog sub-circuits identified as having high fault sensitivity, the method increases simulation thoroughness with more test patterns and deeper analysis, while reducing parameters for less critical sections. This adaptive parameter adjustment optimizes the balance between analog fault detection and computational complexity.
Data Source
AI summary
A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the identified one or more sub-circuits is provided.