Analog Delay Line CDR for Continuous Drift Tracking
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Solution Overview
Problem
Existing clock-data recovery (CDR) circuits in high-speed interfaces, such as MIPI C-PHYSM, face challenges in precisely and continuously tracking changes in delays and clock frequencies due to voltage and temperature drift, leading to quantization errors and inadequate frequency adjustment.
Innovation Solution
The implementation of a clock recovery circuit that uses an analog delay line to continuously and precisely track delay drift, combining a digitally controlled delay with a voltage-controlled delay line to fine-tune the total delay, ensuring seamless adjustments to bit-rate changes and reducing power and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a digitally controlled delay line is used in CDR circuits, then the circuit can track delay changes, but quantization errors occur and frequency adjustment becomes inadequate
Solution Approach 1:
The delay line is segmented into two independent parts: a digitally controlled delay line (DCDL) for coarse delay adjustment and an analog voltage-controlled delay line (VCDEL) for fine continuous adjustment. This segmentation allows each part to specialize in its strength while combining to overcome the limitations of using either alone.
Solution Approach 2:
The patent merges the DCDL and VCDEL into a unified delay tracking system where the DCDL handles integer UI (unit interval) delays and the VCDEL handles fractional UI delays. The combined system provides both the quantization-free operation of digital control and the continuous adjustment capability of analog control.
2Measurement precision
If an analog delay line is used to continuously track delay drift, then precision is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The analog delay line is segmented into two parts with distinct functions: the DCDL for coarse integer UI delay steps and the VCDEL for fine fractional UI delay adjustments. This segmentation reduces the burden on each individual component and simplifies the overall control logic.
Solution Approach 2:
The system dynamically switches between digital and analog control modes based on the required delay adjustment range. The DCDL provides dynamic integer UI steps while the VCDEL provides continuous fine-tuning, creating a hybrid dynamic system that adapts to different operating conditions.
3Area of stationary object
If existing CDR circuits use digital control for delay tracking, then circuit area is reduced, but quantization errors degrade data recovery accuracy
Solution Approach 1:
The delay control system is segmented into digital (DCDL) and analog (VCDEL) portions, where the digital part handles the majority of delay range with small area, and the analog part provides precision correction with minimal area overhead.
Solution Approach 2:
The VCDEL acts as an intermediary between the digital control logic and the analog delay medium, translating digital control signals into precise analog delay adjustments that eliminate quantization errors while maintaining area efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for precise and continuous tracking of clock frequency and delay changes, enhancing the robustness and simplicity of the circuit design while reducing power consumption and circuit area, thereby improving data recovery accuracy.
Implementation Method 1
a shunt capacitor coupled between the first input and ground
Data Source
AI summary
A clock recovery circuit may include a first circuit to produce an output signal that is a logical combination of an edge detection signal and a clock signal. At least some transitions in the edge detection signal may correspond to transitions in a set of data signals. The clock recovery circuit may also include a second circuit to average the output signal to produce a voltage, and a third circuit to add a variable delay to the clock signal based on the voltage.