Analog Variable Delay Conversion to Cycle-Driven Simulation
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Solution Overview
Problem
Current methods for converting analog variable delay in real number modeling code to cycle-driven simulation interface code for digital/mixed-signal emulation are time-consuming, subjective, and inaccurate, making them inefficient for fast system-level verification in full chip integration tasks, especially in scenarios with high interaction between software and analog parts or long algorithms involving digital and analog designs.
Innovation Solution
A method and system that identify and convert analog variable delay into cycle-driven discrete events using a shift register with a bit-length equal to the maximum number of cycles, generating synthesizable code for digital mixed-signal emulation, where the frequency of discrete clock cycles is higher than the Nyquist sampling rate, allowing for accurate mapping of non-fixed delays to clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual conversion of analog emulation tools into synthesizable code is performed, then compatibility with digital emulation tools is achieved, but conversion time increases significantly (up to several days or weeks)
Solution Approach 1:
The conversion process is automated through a computer-implemented method that self-performs the translation of analog variable delay descriptions into cycle-driven simulation interface code, eliminating the need for manual conversion and significantly reducing conversion time while maintaining compatibility
Solution Approach 2:
The manual mechanical conversion process is replaced by an automated computational system that uses algorithms to transform analog delay models into digital simulation code, substituting human effort with machine-based automatic conversion
2Speed
If real number modeling code is used for analog part simulation, then simulation speed increases, but integration target is not achieved in cases with high interaction between SW and analog part
Solution Approach 1:
The invention changes the fundamental parameters of the simulation model by converting continuous real-number analog delay descriptions into discrete cycle-driven events with integer delays, enabling the model to run on digital emulators at higher speeds while maintaining accuracy for software-analog interaction scenarios
Solution Approach 2:
The conversion process dynamically transforms the simulation model based on the specific requirements of digital emulator execution, adapting the analog delay behavior into discrete time steps that maintain fidelity while achieving faster execution speeds on digital hardware
3Productivity
If analog variable delay is converted to cycle-driven discrete events, then emulation speed accelerates by several orders of magnitude, but conversion complexity increases
Solution Approach 1:
The conversion process is segmented into distinct automated steps: identifying analog variable delay descriptions, determining maximum delay values, generating discrete event sequences, and producing synthesizable code. This structured segmentation manages complexity while achieving high-speed emulation
Solution Approach 2:
The invention introduces an automated conversion system that acts as an intermediary between analog variable delay models and cycle-driven simulation interfaces, handling the complex transformation process through systematic algorithmic processing that manages complexity while enabling speed acceleration
Data Source
AI summary
A method and a system for converting a variable delay in real number modeling code to cycle-driven simulation interface event for digital/mixed signal emulation is provided. The method comprises identifying a variable delay of an analog signal in real number modeling code defining an analog circuit; determining a frequency and a maximum number of cycles for a series of discrete clock cycles, wherein the variable delay corresponds to one cycle in the series of discrete clock cycles; converting the variable delay into a plurality of cycle-driven discrete events based on the series of discrete clock cycles; and generating synthesizable code based on the plurality of cycle-driven discrete events for digital mixed signal emulation. A system and a non-transitory computer readable medium to perform the above method are also provided.