Analog Delay Circuit with Phase-Shifted Switching for Ultrasound
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Solution Overview
Problem
Current delay circuits for ultrasonic imaging apparatuses face challenges in achieving high resolution, long maximum delay time, and low power consumption, particularly in two-dimensional probes with numerous channels, where power consumption increases with higher resolution and longer delay times, and synchronization among channels is not adequately addressed.
Innovation Solution
A delay circuit configuration that includes a plurality of analog signal memory devices, sampling switches, and output switches controlled by a clock generation part, allowing for phase shifting of sampling and output switch control signals to achieve higher resolution and longer delay times with reduced power consumption, and ensuring synchronization among channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock frequency is raised to achieve higher delay resolution, then the delay resolution is improved, but the power consumption increases
Solution Approach 1:
The delay circuit is divided into multiple stages, each handling a portion of the total delay range. This segmentation allows each stage to operate at lower frequencies while achieving the same overall resolution, thereby reducing power consumption while maintaining delay precision.
Solution Approach 2:
The patent transitions from a single-dimensional approach (increasing clock frequency) to a multi-dimensional solution by combining multiple delay stages with different resolution levels. This allows achieving high resolution without proportionally increasing power consumption across the entire system.
2Duration of action of moving object
If the number of parallel-connected capacities is increased to achieve longer maximum delay time and higher resolution, then the delay capability is improved, but the power consumption and circuit complexity increase
Solution Approach 1:
The delay circuit is divided into multiple stages, each handling a portion of the total delay range. This segmentation allows each stage to operate at lower frequencies while achieving the same overall resolution, thereby reducing power consumption while maintaining delay precision.
Solution Approach 2:
Multiple delay stages are nested within each other, with each stage providing a subset of the total delay range. This nested structure allows the circuit to achieve long maximum delay times without requiring all capacities to be actively driven at full power simultaneously.
3Measurement precision
If multiple delay circuits are series-connected to achieve higher resolution and longer delay time, then the delay performance is improved, but the power consumption increases due to additive effect
Solution Approach 1:
Multiple delay stages are merged into a unified circuit architecture with shared control logic and power management. This merging allows the circuit to achieve high resolution and long delay times while avoiding the additive power consumption that would result from completely separate delay circuits.
4Measurement precision
If the hold time of sample holding means is controlled to generate small delays, then the delay resolution is improved, but the analog signal characteristics are deteriorated
Solution Approach 1:
The delay function is segmented across multiple stages, allowing small delay increments to be achieved through coordinated operation of multiple switches rather than relying on precise hold time control of a single sample holding circuit. This reduces the impact on analog signal characteristics.
Data Source
AI summary
A delay circuit and an ultrasonic imaging apparatus with the higher-accuracy delay time, the longer maximum delay time, and the lower power consumption are provided. An input line to which an analog input signal is input, a plurality of analog signal memory devices, an output line, a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices, a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line, and a clock generation part that generates sampling switch control signals for controlling the sampling switches and output switch control signals for controlling the output switches are provided, and phase of the sampling switch control signals may be shifted with respect to phase of the output switch control signals.