Analog-to-Digital Converter Resolution via Parallel Conversion
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Solution Overview
Problem
Ramp-type analog/digital converters face limitations in increasing resolution without prolonging processing time, as a 2-bit increase in resolution quadruples the conversion duration, making it challenging to achieve high-speed image sensors with large pixel matrices and high data rates.
Innovation Solution
The method involves performing two simultaneous analog/digital conversions of 10 bits each with different full-scale values, where the second conversion has a full-scale value four times higher, and using digital post-processing to generate a 12-bit digital word without extending the processing time, allowing for independent operation of each converter with its own reset and capacitive connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of a ramp-type analog/digital converter is increased from 10 to 12 bits, then the conversion precision is improved, but the conversion duration increases by a factor of 4
Solution Approach 1:
The patent divides a single high-resolution conversion into multiple lower-resolution parallel conversions. Two 10-bit converters process the same analog signal simultaneously with different full-scale ranges, producing intermediate results that are combined through digital post-processing to achieve 12-bit resolution without extending conversion time.
Solution Approach 2:
The patent transitions from a single-timepoint conversion to a multi-timepoint approach where conversions occur in parallel across different operational dimensions. By using converters with different full-scale values operating simultaneously, the system achieves higher resolution through spatial-temporal distribution rather than sequential processing.
2Productivity
If the resolution of analog/digital converters is increased to achieve high-speed image sensors with large pixel matrices, then the data rate and sensor performance are improved, but the processing time and system complexity increase
Solution Approach 1:
The patent merges multiple 10-bit conversion results through digital post-processing to produce a unified 12-bit digital word. By combining the intermediate results from parallel converters using logical operations and bit manipulation, the system achieves high-resolution conversion without the time penalty of sequential processing.
Solution Approach 2:
The patent replaces analog time-multiplexed conversion with a parallel digital processing approach. Instead of using a single converter that sequentially handles different bit resolutions, the system uses multiple converters operating in parallel with their results combined through digital logic, eliminating the time multiplication effect.
3Speed
If two analog/digital converters operate simultaneously with different full-scale values, then the conversion speed is maintained, but the device complexity increases
Solution Approach 1:
The patent makes the converter system multi-functional by enabling two converters with different full-scale ranges to process the same input signal simultaneously. This universal approach allows the system to handle a wider dynamic range and achieve higher resolution while maintaining the same conversion time, as each converter can operate independently with its optimized full-scale value.
Data Source
AI summary
A method includes a first analog/digital conversion of an analog signal over m bits, with m less than n, associated with a first full-scale value, and a second analog/digital conversion of the analog signal over m bits associated with a second full-scale value 2n-m times bigger than the first. The two analog/digital conversions are carried out simultaneously and respectively delivering a first intermediate digital word of m bits and a second intermediate digital word of m bits. The method also includes a digital post-processing carried out after the two analog/digital conversions and generating an n-bit digital word starting from at least one of the two intermediate digital words extended to n bits and from at least one threshold digital indication representative of at least one threshold lower than or equal to the first full-scale value.