Analog Divider Test Circuit with Parallel Readout
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Solution Overview
Problem
Existing methods for testing divider circuits in analog integrated circuits are excessively time-consuming due to the lack of compatibility with boundary scan circuitry, particularly in analog dividers that include non-standard flip-flop circuits.
Innovation Solution
On-chip systems with test-mode functionality are introduced, enabling flip-flop observability and efficient testing through readout functionality, allowing simultaneous configuration and readout of multiple dividers in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If existing testing methods are used for divider circuits in analog integrated circuits, then the testing can be performed, but the testing time is excessively long
Solution Approach 1:
The testing process is segmented into distinct phases: pre-loading the divider circuit with an initial value, clocking the circuit for a predetermined number of cycles, and reading the final output value. This segmentation allows for systematic testing and enables parallel processing of multiple dividers simultaneously, thereby reducing overall testing time while maintaining thoroughness.
2Productivity
If boundary scan circuitry is used for testing, then testing efficiency can be improved, but analog integrated circuits with non-standard flip-flop circuits are not compatible with boundary scan circuitry
Solution Approach 1:
The testing methodology is designed to be universally applicable to analog divider circuits regardless of their internal flip-flop implementation. By using a functional testing approach that relies on the divider's input-output behavior rather than its internal structure, the method achieves compatibility with non-standard flip-flop circuits while maintaining high testing efficiency through parallel processing capabilities.
3Measurement precision
If wide bit-width divider circuits are tested using existing methods, then all bits can be tested, but the testing process becomes excessively time-consuming
Solution Approach 1:
Multiple divider circuits are tested simultaneously by providing them with the same initial value and clocking them in parallel. Each divider's output is read independently, allowing comprehensive testing of wide bit-width circuits without sequentially processing each bit, thereby maintaining measurement precision while dramatically reducing testing time.
Data Source
AI summary
A divider circuit includes an analog divider circuit with pre-load circuitry configured to allow for a programmable starting value. The circuit is responsive, synchronous with a divider clock, to count from the starting value, and includes an observation bus that outputs a current count value of the analog divider circuit. The divider circuit further includes test clock logic configured, in a divider circuit test mode, to be responsive to a reference clock to output the divider clock to clock the analog divider circuit for a number of clock cycles corresponding to a programmable test clock length.