Analog Duty Cycle Correction Loop Using Clock Averaging
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Solution Overview
Problem
Existing duty cycle correction techniques rely on digital delay elements, which may not be suitable for applications requiring an analog loop, limiting their effectiveness in certain scenarios.
Innovation Solution
A duty cycle correction loop using clock averaging and voltage comparisons to determine whether to increase or decrease a delay, employing analog delay elements and a phase control circuit to select between the clock signal and its inverted version, with a duty cycle adjustment generator to ensure a 50% duty cycle, utilizing comparators and a multiplexer to adjust the duty cycle within predetermined voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital delay elements are used for duty cycle correction, then the correction can be implemented with digital circuits, but the solution is not suitable for applications requiring an analog loop
Solution Approach 1:
The patent replaces digital delay elements with analog delay elements (such as RC circuits or current-mode delay circuits) to enable duty cycle correction in analog loop applications. This substitution allows the correction mechanism to operate within analog domains while maintaining the fundamental feedback loop structure.
Solution Approach 2:
The patent changes the operational parameters from digital logic levels to analog voltage or current parameters. The duty cycle correction is achieved by continuously adjusting analog delay parameters based on feedback from duty cycle detection, enabling seamless integration into analog loop architectures.
2Measurement precision
If the duty cycle correction loop responds to all duty cycle deviations, then precise correction can be achieved, but oscillations may occur reducing stability
Solution Approach 1:
The patent implements a dead zone or threshold-based response where the correction loop only acts when duty cycle deviations exceed predetermined thresholds. This partial action approach prevents the loop from responding to minor fluctuations, thereby avoiding oscillations while maintaining correction precision for significant deviations.
Solution Approach 2:
The patent employs feedback mechanisms where the output of the duty cycle correction is monitored and fed back to adjust the correction amount. This feedback control prevents over-correction and stabilizes the loop by reducing the correction gain when the system approaches the target duty cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively generates a duty cycle corrected clock signal, ensuring optimal performance by adjusting the duty cycle based on precise voltage comparisons, preventing oscillations and maintaining stability within a programmable error range.
Implementation Method 1
determining whether a clock signal has a duty cycle greater than 50% based on averaging the clock signal
Implementation Method 2
comparing that averaged clock signal to a high voltage supply (e.g. 1/2 VDD)
Implementation Method 3
The first averaging clock circuit (e.g. an RC circuit) can receive the clock signal
Data Source
AI summary
Providing duty cycle correction can include determining whether a clock signal has a duty cycle greater than 50% based on averaging the clock signal and comparing that averaged clock signal to ½ VDD. When the duty cycle is greater than 50%, the clock signal can be selected. When the duty cycle is less than 50%, the inverted clock signal can be selected. Thus, a duty cycle corrected clock signal can be generated based on the clock signal or the inverted clock signal. Notably, a duty cycle control signal can be adjusted based on comparisons of an averaged, duty cycle corrected clock signal and predetermined low/high voltage ranges. Components performing comparing functions can be strobed based on a count performed on the clock signal.