Analog Duty-Cycle Detection Circuit Without High-Speed Clocks
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Solution Overview
Problem
Existing duty-cycle detection methods for communication protocols like CAN-XL are expensive due to the use of high-speed precision clocks and counters, which are costly and inefficient.
Innovation Solution
An analog duty-cycle detector circuit is introduced, comprising off-time and on-time detection circuitry, compare circuitry, and a controller, utilizing transistors and capacitors to detect duty-cycle without the need for high-speed clocks, enabling efficient duty-cycle detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a counter and high-speed precision clock are used for duty-cycle detection, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces the digital counting mechanism (mechanical/electronic system) with an analog time-charge system. The duty cycle is detected by charging capacitors during the high and low periods of the input signal, then comparing the charges. This substitution eliminates the need for high-speed clocks and counters, reducing circuit complexity while maintaining detection accuracy.
Solution Approach 2:
The patent transforms the duty-cycle measurement problem from a digital count-based approach to an analog time-charge approach. By changing the measurement parameter from discrete clock cycles to continuous charge accumulation time, the system achieves accurate duty-cycle detection without requiring high-speed digital components.
2Measurement precision
If a counter and high-speed precision clock are used for duty-cycle detection, then measurement precision is improved, but cost increases
Solution Approach 1:
The patent uses simple, inexpensive analog components (capacitors, resistors, transistors) instead of expensive high-speed digital components. The capacitors serve as temporary charge storage elements that are repeatedly charged and discharged, providing a low-cost solution for time measurement that eliminates the need for costly precision clocks and counters.
3Device complexity
If an analog duty-cycle detector circuit is used, then device complexity is reduced, but measurement precision may worsen
Solution Approach 1:
The patent combines multiple functions into the analog comparator circuit: time measurement, charge comparison, and duty-cycle determination all occur in a single integrated analog processing stage. This merging of functions simplifies the overall circuit architecture while maintaining precise duty-cycle detection through the physical comparison of charge magnitudes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The analog duty-cycle detector circuit effectively detects duty-cycles, reducing costs and improving efficiency by eliminating the requirement for high-speed precision clocks, thus enhancing the reliability and cost-effectiveness of duty-cycle detection in communication protocols.
Implementation Method 1
The first capacitor has a first terminal and a second terminal. The second terminal of the first transistor is coupled to the first terminal of the first capacitor.
Implementation Method 2
The second capacitor has a first terminal and a second terminal. The second terminal of the second transistor is coupled to the first terminal of the second capacitor.
Implementation Method 3
The compare circuitry has a first terminal, a second terminal, and a third terminal. The first terminal of the compare circuitry is coupled to the third terminal of the off-time detection circuitry. The second terminal of the compare circuitry is coupled to the third terminal of the on-time detection circuitry.
Data Source
AI summary
An analog duty-cycle detector includes: off-time detection circuitry; on-time detection circuitry; compare circuitry; and a controller. The off-time detection circuitry includes a first transistor and a first capacitor. The on-time detection circuitry includes a second transistor and a second capacitor. The compare circuitry has a first terminal, a second terminal, and a third terminal. The first terminal of the compare circuitry is coupled to a first terminal of the first capacitor. The second terminal of the compare circuitry is coupled to a first terminal of the second capacitor. The controller has a first terminal and a second terminal. The first terminal of the controller coupled to a control terminal of the first transistor. The second terminal of the controller coupled to the control terminal of the second transistor.