Analog Duty Cycle Correction for IQ Mixer Image Rejection
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Solution Overview
Problem
Zero intermediate frequency (ZIF) architectures in wireless transmitters and receivers face challenges due to imperfect quadrature generation, leading to image rejection issues caused by phase and amplitude mismatches in in-phase (I) and quadrature-phase (Q) signals, which are not effectively addressed by existing digital correction methods that are power-hungry and unsuitable for high-frequency operations.
Innovation Solution
Analog duty cycle correction loops are implemented to adjust the duty cycle of clock signals before quadrature divide-by-two circuitry, using analog tuning loops to track and correct dynamic differential errors, reducing quadrature errors and improving image rejection in receivers and transmission performance in transmitters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital correction methods are used to correct quadrature errors, then image rejection can be improved, but power consumption increases significantly
Solution Approach 1:
The patent replaces digital correction methods with an analog duty cycle correction circuit. The analog circuit uses continuous voltage signals to adjust the duty cycle of clock signals, thereby correcting quadrature errors without requiring power-hungry digital signal processing. This substitution of analog for digital mechanisms directly resolves the contradiction between image rejection performance and power consumption.
Solution Approach 2:
The patent changes the operating parameter from digital domain correction to analog domain duty cycle adjustment. By continuously adjusting the duty cycle parameter of the clock signals in the analog domain, the system achieves quadrature error correction with much lower power consumption compared to digital correction methods, while maintaining effective image rejection.
2Measurement precision
If digital tracking algorithms are used to correct dynamic quadrature errors, then correction accuracy can be improved, but circuit complexity and power consumption increase
Solution Approach 1:
The patent substitutes complex digital tracking algorithms with a relatively simple analog duty cycle correction circuit. The analog circuit continuously tracks and corrects quadrature errors using voltage-based feedback mechanisms, achieving dynamic correction accuracy without the complexity of digital signal processing algorithms and associated hardware.
3Device complexity
If ZIF architecture is used to remove filters and intermediate mixer stages, then device complexity is reduced, but image rejection becomes more sensitive to I and Q balance
Solution Approach 1:
The patent applies preliminary action by correcting the duty cycle of clock signals before they are used to generate I and Q signals. The analog duty cycle correction circuit pre-adjusts the clock signals to ensure accurate quadrature generation, preventing image rejection degradation at the source rather than requiring complex post-processing or additional filtering stages.
Solution Approach 2:
The patent implements a feedback mechanism where the analog duty cycle correction circuit continuously monitors and adjusts the clock signal duty cycles based on detected quadrature errors. This closed-loop feedback ensures maintained I and Q balance despite variations in operating conditions, preserving image rejection performance in the simplified ZIF architecture.
Data Source
AI summary
Systems, devices, and methods related to frequency converter arrangements are provided. For example, a frequency converter arrangement converts a first signal centered at a first frequency to a second signal centered at a second frequency different from the first frequency. The frequency converter arrangement includes local oscillator (LO) circuitry and in-phase, quadrature-phase (IQ) mixer circuitry coupled to the LO circuitry. The LO circuitry includes duty cycle correction circuitry to adjust a duty cycle of a pair of input clock signals. The duty cycle correction circuitry includes coarse tuning circuitry responsive to a digital calibration code, and analog tuning loop circuitry. The LO circuitry further includes quadrature divider circuitry coupled to an output of the duty cycle correction circuitry, where the quadrature divider circuitry generates an in-phase LO signal and a quadrature-phase LO signal from a pair of output clock signals at outputs of the duty cycle correction circuitry.