Analog Echo Cancellation Subtraction Circuit for High Speed Full Duplex Data

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Solution Overview

Problem

Existing high-speed echo cancellation solutions for full duplex data transmissions, such as those using analog-to-digital converters, face limitations in speed and bandwidth due to digital processing, which is inadequate for effectively eliminating echoes in bi-directional communication systems.

Innovation Solution

Analog echo cancellation is achieved through a subtraction circuit with capacitors and a termination circuit that directly processes differential nodes to eliminate echo signals, bypassing the need for digital conversion, and a filter circuit to address signal mismatches and glitches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If digital echo cancellation using ADCs is used, then echo cancellation is achieved, but speed and bandwidth are limited

Engineering Contradiction:

Improveecho cancellation accuracyVSAvoiddata transmission speed

Core Design Contradiction:

Measurement precisionVSSpeed

Solution Approach 1:

The patent replaces the digital signal processing system (ADCs and digital echo cancellation algorithms) with an analog subtraction circuit that directly subtracts the transmitted signal from the received signal in the analog domain. This substitution eliminates the speed and bandwidth limitations inherent in digital conversion and processing, while maintaining echo cancellation functionality through continuous analog operation.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operational domain from digital to analog by modifying the signal processing parameters. Instead of converting signals to digital form for processing, the system maintains signals in their native analog form throughout the cancellation process, enabling higher speed and bandwidth operation while preserving echo cancellation accuracy.

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If digital echo cancellation using ADCs is used, then echo cancellation is achieved, but bandwidth is limited

Engineering Contradiction:

Improveecho cancellation accuracyVSAvoidbandwidth

Core Design Contradiction:

Measurement precisionVSQuantity of substance

Solution Approach 1:

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If analog subtraction circuit is used, then speed and bandwidth are improved, but signal mismatches and glitches occur

Engineering Contradiction:

Improvedata transmission speedVSAvoidsignal accuracy

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent incorporates a feedback mechanism where the output of the analog subtraction circuit is monitored and fed back to adjust the cancellation process. This feedback loop detects and corrects signal mismatches and glitches in real-time, ensuring that the high-speed analog processing maintains signal accuracy and reliability.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent introduces an intermediary filtering stage between the analog subtraction circuit and the output. This intermediary component smooths out glitches and corrects minor signal mismatches that occur during high-speed analog processing, thereby maintaining signal reliability without compromising the speed advantages of the analog approach.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10116428B2Echo cancellation for high speed full duplex data transmissions

Publication Date: 2018.10.30 LATTICE SEMICON CORP

AI summary

Systems, devices and methods for analog echo cancellation for high speed full duplex data transmissions, which include a first set of differential nodes to receive reception data and transmission data, a second set of differential nodes to receive the transmission data, and a subtraction circuit to receive data from the first set of differential nodes and data from the second set of differential nodes. The subtraction circuit includes a plurality of capacitors to receive data from each of the first and second sets differential nodes, and a termination circuit for providing DC termination voltage to subtract the data of the second set of differential nodes from the data of the first set of differential nodes to eliminate echo from the reception data received at the first set differential nodes.