Analog Edge AI Computing with MEMS CTRNNs and In-Situ Training

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Solution Overview

Problem

Existing digital AI computing systems for edge applications are inefficient due to analog-to-digital and digital-to-analog conversion burdens and processing bottlenecks, and in-situ training for edge applications is challenging, particularly with conventional stochastic gradient descent approaches.

Innovation Solution

Analog computing using MEMS devices, specifically MEMS CTRNNs, that perform edge AI computing with reduced power and increased speed by eliminating conversion burdens and enabling in-situ training through difference target propagation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If digital computing approaches are used for edge AI computation, then processing capability is provided, but power consumption is excessive and conversion bottlenecks occur

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing efficiency
Core Design Contradiction:
PowerVSProductivity

Solution Approach 1:

The patent replaces the digital computing system with an analog computing system that directly processes analog signals. This substitution eliminates the need for ADC and DAC conversions, thereby reducing power consumption while maintaining processing capability for edge AI applications.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental operating parameter from digital discrete values to analog continuous values. By using analog signals to represent and process information, the system achieves lower power consumption and eliminates conversion bottlenecks inherent in digital systems.

Inventive Principle:
Principle #35Parameter changes

2Speed

If analog-to-digital and digital-to-analog conversions are performed, then digital processing is enabled, but processing speed decreases and bottlenecks occur

Engineering Contradiction:
Improveprocessing speedVSAvoidconversion complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent extracts and removes the ADC and DAC conversion stages from the signal processing chain. By directly processing analog signals through analog computing components, the system eliminates conversion bottlenecks and achieves faster processing speed.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent substitutes the digital conversion and processing mechanism with a direct analog processing mechanism. This replacement eliminates the speed-limiting conversion steps while reducing overall system complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If conventional SGD learning approach is used, then training capability is provided, but implementation in analog hardware is difficult

Engineering Contradiction:
Improvetraining capabilityVSAvoidimplementation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent changes the training algorithm from conventional SGD to a variant that is natively compatible with analog hardware. This parameter change in the learning approach enables direct implementation on analog devices while maintaining training capability.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a training mechanism that leverages the inherent properties of analog hardware rather than forcing digital algorithms onto analog systems. The analog hardware's natural characteristics are utilized to perform learning operations, simplifying implementation.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP4700598A1Analog system for edge artificial intelligence computing
Publication Date: 2026.02.25 GE AVIATION SYSTEMS LLC
  • EP4700598A1 patent drawingFigure 1
  • EP4700598A1 patent drawingFigure 2
  • EP4700598A1 patent drawingFigure 3~4

AI summary

An analog system for edge artificial intelligence computing includes a first plurality of analog edge devices (102) configured to receive an input analog signal (100) and to output a first plurality of output analog signals (103), a second plurality of analog edge devices (104) configured to receive the first plurality of output analog signals (103) and to output a second plurality of output analog signal (105), and one or more memory devices (208) in communication with the first plurality of analog edge devices (102) and the second plurality of analog edge devices (104), and configured to store weight parameters, the weight parameters being adjustable based on time constants of the first plurality of analog edge devices (102) or the second plurality of analog devices (104), or both. The second plurality of output analog signals (105) are multiplied by the weight parameters to obtain a plurality of weighted analog signals.