Analog FIR Feedforward DFE for Low-Power SerDes Equalization

Solution Overview

Problem

High-speed serializer/deserializer (SerDes) communication systems face challenges in compensating for distortions and reflections in transmission lines due to inter-symbol interference, leading to increased power consumption and area usage, especially at higher bitrates, as traditional loop unrolled circuits require numerous data slicers and analog-to-digital converters.

Innovation Solution

Implementing an analog finite impulse response (FIR) filter as a feedforward branch to generate a feedforward signal for the first tap of a decision feedback equalizer (DFE), reducing the need for loop unrolling and pre-computation, thereby minimizing area and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional loop unrolled circuits are used to compensate for inter-symbol interference, then equalization performance is improved, but power consumption and area usage increase significantly

Engineering Contradiction:

Improveequalization performanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts only the essential equalization function needed to compensate for inter-symbol interference, implementing it through a simplified continuous-time linear equalizer (CTLE) circuit rather than using the complete but resource-intensive loop unrolled circuit. This extraction approach maintains adequate equalization performance while dramatically reducing power consumption and circuit area.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the operational parameters of the equalizer by using continuous-time processing instead of discrete-time processing. The CTLE operates continuously on the analog signal, adjusting equalization parameters dynamically without requiring the complex digital processing stages of traditional loop unrolled circuits, thereby reducing power consumption while maintaining performance.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If traditional loop unrolled circuits are used to compensate for inter-symbol interference, then equalization performance is improved, but circuit area increases

Engineering Contradiction:

Improveequalization performanceVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts only the essential equalization function needed to compensate for inter-symbol interference, implementing it through a simplified continuous-time linear equalizer (CTLE) circuit rather than using the complete but resource-intensive loop unrolled circuit. This extraction approach maintains adequate equalization performance while dramatically reducing power consumption and circuit area.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent substitutes the mechanical/digital processing system (loop unrolled circuits with data slicers and ADCs) with an analog continuous-time system (CTLE). This substitution eliminates the need for complex digital logic and conversion circuits, significantly reducing the required circuit area while maintaining equalization functionality.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If higher bitrates are used in SerDes communication, then data transmission speed is improved, but timing constraints become more difficult to meet

Engineering Contradiction:

Improvedata transmission speedVSAvoidtiming constraint complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent substitutes the mechanical/digital processing system (loop unrolled circuits with data slicers and ADCs) with an analog continuous-time system (CTLE). This substitution eliminates the need for complex digital logic and conversion circuits, significantly reducing the required circuit area while maintaining equalization functionality.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements continuous equalization processing that operates throughout the entire signal transmission process without discrete sampling or conversion stages. This continuous operation allows the circuit to adapt dynamically to timing variations at higher bitrates, simplifying timing constraint management while maintaining transmission speed.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS12413454B1Decision feedback equalizer with feedforward finite impulse response filter

Publication Date: 2025.09.09 SYNOPSYS INC

AI summary

An equalizer circuit includes: an analog front end circuit configured to receive an analog input signal from a transmission line; an analog finite impulse response filter circuit including: a sample and hold circuit configured to sample an output of the analog front end circuit; and a weighting circuit configured to weight the output of the analog front end circuit to generate a feedforward signal; and a decision feedback equalizer circuit configured to receive an output of the analog front end circuit and the feedforward signal.