Analog FPGA Chip Verification Structure for Hybrid Design Accuracy
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Solution Overview
Problem
Current chip design verification methods, particularly for digital-analog hybrid chips, face challenges in achieving accurate verification due to differences between simulated and actual chip interfaces and functions, leading to poor verification accuracy and prolonged verification periods.
Innovation Solution
A chip verification structure and method that utilizes an analog chip connected to an FPGA chip via multiple interfaces, including IO and communication protocol interfaces, to simulate both analog and digital function modules, reducing interface differences and improving verification accuracy by using a control module and register file for signal processing and error checking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete circuits are used to simulate analog function modules, then verification can be performed, but verification accuracy deteriorates due to interface and function differences from actual chips
Solution Approach 1:
The patent creates a copy of the actual chip structure using an analog chip that mirrors the homologous analog module architecture. This copy includes identical interface structures and communication protocols, allowing verification without discrete circuits. The analog chip is designed to be structurally homologous with the target chip's analog modules, preserving interface characteristics while enabling accurate verification.
Solution Approach 2:
The verification system is segmented into distinct functional components: an analog chip for analog module verification, an FPGA chip for digital module verification, and a control module for coordination. This segmentation allows each component to be optimized for its specific function while maintaining overall system accuracy, avoiding the need to use discrete circuits for the entire analog verification process.
2Productivity
If separate verification methods are used for digital and analog modules, then verification can be conducted, but verification period increases due to multiple verification processes
Solution Approach 1:
The patent merges the verification processes for digital and analog modules into a single integrated system. The analog chip and FPGA chip are connected through standardized interfaces and controlled by a unified control module, allowing simultaneous verification of both module types. This integration eliminates the need for separate verification processes and reduces the overall verification period.
Solution Approach 2:
The control module is designed with multi-functionality to manage both analog and digital verification processes. It can control the analog chip for analog module verification, the FPGA chip for digital module verification, and coordinate between them. This universal control mechanism enables a single verification system to handle multiple verification tasks efficiently, reducing the verification period.
Data Source
AI summary
Disclosed are a chip verification structure, a chip verification system, and a chip verification method. The chip verification structure includes an analog chip, the analog chip includes at least one analog module. Since the analog chip is homologous with the sample of the chip design, a functional difference between the analog chip and the analog function module of the chip design may be reduced. Since the analog chip is connected to the FPGA chip via the plurality of types of interfaces, a difference between an interface of the analog chip and the FPGA chip and an interface of the analog function module and the digital function module of the chip design may be reduced, so that a verification accuracy of the chip design may be improved and a verification period of the chip design may be reduced.