Analog Neural Net FPGA Routing Using Pulse-Width Signal Conversion

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Analog neural network integrated circuits face challenges in routing variable voltages due to the need for operational amplifiers, which introduce errors and consume significant power and die area, making them expensive and inflexible, while digital-analog conversions are costly and error-prone.

Innovation Solution

The solution involves converting analog quantities into analog timing pulses for routing through switch points, using a charge-to-pulse-width converter circuit and programmable Vt transistors, eliminating the need for operational amplifiers and reducing linearity requirements, and utilizing a user-programmable routing network with interconnect conductors and matrix vector multipliers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If operational amplifiers are used to buffer analog voltages for routing, then routing capability is achieved, but power consumption and die area increase significantly

Engineering Contradiction:
Improverouting capabilityVSAvoidpower consumption
Core Design Contradiction:
Ease of operationVSUse of energy by stationary object

Solution Approach 1:

The patent extracts the buffering function from operational amplifiers and implements it using simple transistor switches in an FPGA routing network. Instead of using complex op-amps to buffer analog voltages, the invention routes analog signals directly through programmable transistor switches that can open or close connections without requiring active buffering, thereby eliminating the power consumption and die area overhead of operational amplifiers.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces expensive, power-hungry operational amplifiers with simple, low-cost transistor switches that consume minimal power. These transistor-based routing elements are much cheaper in terms of both die area and power consumption, sacrificing the high-precision buffering capability of op-amps for a simpler switching mechanism that is sufficient for the application.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Ease of operation

If operational amplifiers are used to buffer analog voltages for routing, then routing capability is achieved, but die area consumption increases

Engineering Contradiction:
Improverouting capabilityVSAvoiddie area
Core Design Contradiction:
Ease of operationVSArea of stationary object

Solution Approach 1:

The patent extracts the buffering function from operational amplifiers and implements it using simple transistor switches in an FPGA routing network. Instead of using complex op-amps to buffer analog voltages, the invention routes analog signals directly through programmable transistor switches that can open or close connections without requiring active buffering, thereby eliminating the power consumption and die area overhead of operational amplifiers.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces expensive, power-hungry operational amplifiers with simple, low-cost transistor switches that consume minimal power. These transistor-based routing elements are much cheaper in terms of both die area and power consumption, sacrificing the high-precision buffering capability of op-amps for a simpler switching mechanism that is sufficient for the application.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Adaptability or versatility

If digital-to-analog converters are used for interface conversion, then digital-analog interfacing is achieved, but cost and error rate increase

Engineering Contradiction:
Improveinterface conversion capabilityVSAvoiderror rate
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent extracts the conversion function from complex digital-to-analog converters and implements it using simple transistor switches that directly interface digital control signals with analog voltage lines. Instead of using DACs to generate analog voltages from digital codes, the invention uses digitally-controlled transistor switches to select and pass through analog voltages already present on the lines, eliminating the conversion errors and cost of DACs.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses digital control signals to control transistor switches that copy or select analog voltages from one line to another. Instead of converting digital values to analog voltages through DACs, the digital control simply selects which analog voltage to pass through the transistor switch, maintaining the original analog signal integrity while achieving digital-analog interfacing functionality.

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces errors, power consumption, and costs by eliminating the need for operational amplifiers and digital-to-analog conversions, while maintaining the efficiency of analog computation with improved flexibility and accuracy.

Implementation Method 1

Conversion from voltage to time employs a capacitor charged to an analog voltage which capacitor is discharged by a current source and generates a pulse having a width representing the analog voltage

Methodology Applied
Scientific EffectCapacitor charging: Capacitance

Implementation Method 2

a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network

Methodology Applied
Scientific EffectComparator detection:

Data Source

PatentUS11023559B2Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit
Publication Date: 2021.06.01 MICROSEMI SOC CORP
  • US11023559B2 patent drawing
  • US11023559B2 patent drawing
  • US11023559B2 patent drawing

AI summary

A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.