Analog Front-End Pin Sharing With Shared Negative Reference
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Solution Overview
Problem
Display system chips face inefficiencies in pin usage due to the need for separate pins for each negative signal in differential signal processing, leading to increased costs and complexity in redistributing DC levels for positive and negative signals.
Innovation Solution
An analog front-end processing apparatus and method that shares pins by fixing all negative signals at a reference voltage, using positive clamping circuits for target positive voltages and a negative clamping circuit for a shared reference voltage, allowing sample and hold circuits to adjust and maintain the correct voltage differences between target positive and negative voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate negative pins are used for each negative signal to maintain correct DC levels, then signal integrity is ensured, but the number of pins increases and cost increases
Solution Approach 1:
The patent merges multiple negative signal paths into a single shared negative pin by using a common negative reference voltage (VREF1) for all differential signal pairs. The negative clamping circuit couples all negative signals to this shared reference, allowing multiple channels to share one physical pin while maintaining individual signal integrity through the sample and hold circuits that preserve voltage differences.
Solution Approach 2:
The patent introduces sample and hold circuits as intermediary elements between the shared negative pin and the differential signal pairs. These circuits capture and maintain the voltage difference between positive and negative signals during the sample period, then hold this difference during the hold period, enabling pin sharing while preserving signal integrity. The reference voltage circuit also acts as an intermediary by providing stable reference voltages to the clamping circuits.
2Ease of manufacture
If separate negative pins are used for each negative signal, then DC level control is simplified, but device complexity and cost increase
Solution Approach 1:
The shared negative pin serves multiple functions: it provides the negative reference for all differential signal pairs simultaneously, acts as a common return path for multiple channels, and enables DC level control for all channels through a single clamping circuit. This multi-functionality reduces pin count while maintaining the ability to control DC levels of each channel independently through the sample and hold circuits.
Solution Approach 2:
The patent changes the control parameter from individual negative pin voltages to a shared reference voltage (VREF1) that is coupled to all negative signals through the negative clamping circuit. The DC level control is achieved by adjusting the reference voltage parameters rather than controlling each negative pin separately, simplifying the overall system while maintaining channel independence through the sample and hold voltage differences.
3Quantity of substance
If all negative signals are fixed at a shared reference voltage, then pin count is reduced, but maintaining voltage differences between target positive and negative voltages becomes more challenging
Solution Approach 1:
The patent applies preliminary action by having the sample and hold circuits capture the voltage difference between target positive and negative voltages during the sample period before any pin sharing occurs. This pre-captured voltage difference is then held during the hold period, ensuring that even though all negative signals share a common reference voltage, the individual voltage differences required for each channel are preserved through the preliminary sampling action.
Solution Approach 2:
The sample and hold circuits provide a feedback mechanism that maintains the voltage difference between target positive and negative voltages. By continuously sampling the voltage difference during the sample period and holding it during the hold period, the system creates a feedback loop that ensures the voltage differences remain accurate even with the shared reference voltage, thereby maintaining manufacturing precision.
Data Source
AI summary
An analog front-end processing apparatus capable of sharing pins includes a plurality of positive pins, a negative pin, a plurality of positive clamping circuits, a negative clamping circuit, a plurality of sample and hold circuits and a plurality of adjusting circuits. The positive clamping circuits have positive signals fixed at their corresponding target positive voltages. The negative clamping circuit has a negative signal fixed at a first reference voltage. Each sample and hold circuit has a positive input terminal and a negative input terminal, wherein a voltage difference between the two input terminals is substantially equal to a voltage difference between the corresponding target positive voltage and the first reference voltage during a sample period, and a voltage difference between the two input terminals is equal to a voltage difference between the corresponding target negative voltage and a second reference voltage during a hold period.