Analog Circuit Graph Verification for Post-Silicon Equivalence
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Solution Overview
Problem
Current post-silicon verification and validation techniques for analog, mixed-signal, and RF designs lack effective tools and methods to ensure equivalence to trusted golden designs, as they do not adequately account for performance and physics-related changes beyond logical failures.
Innovation Solution
A novel system and method that represents circuits as graphs, leveraging graph theory to perform post-silicon verification and validation by analyzing schematic and parasitic levels, using parametric graph isomorphism to detect deviations in circuit topology and component parameters, and applying graph reduction techniques to reduce computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital design verification and validation techniques are applied to analog designs, then equivalence checking can be performed across multiple modalities, but the techniques do not adequately capture performance and physics-related changes in analog circuits
Solution Approach 1:
The patent transforms analog circuit verification from binary equivalence checking to continuous parameter analysis. It extracts and compares electrical parameters (voltage, current, frequency) and physical parameters (transistor dimensions, material properties) between golden and recovered designs, enabling detection of subtle performance deviations that digital techniques miss.
Solution Approach 2:
The patent adds new verification dimensions beyond logical equivalence. It introduces electrical domain verification (I-V characteristics, frequency response) and physical domain verification (layout geometry, material properties), creating a multi-dimensional verification framework that comprehensively assesses analog design equivalence.
2Reliability
If comprehensive analysis of electrical and physical domains is performed to ensure high-confidence assurance, then design deviations can be accurately detected, but computational complexity and analysis time increase significantly
Solution Approach 1:
The patent divides the verification process into distinct modular stages: extraction stage (separating electrical and physical parameter extraction), comparison stage (independent comparison modules for different parameter types), and analysis stage (deviation detection and assurance metric calculation). This segmentation allows each module to be optimized independently and facilitates parallel processing.
Solution Approach 2:
The patent introduces an intermediary data structure that stores extracted parameters in a standardized format before comparison. This intermediary representation layer decouples the extraction and comparison operations, enabling flexible implementation of different extraction and comparison algorithms without increasing overall system complexity.
Data Source
AI summary
In an approach to post-silicon analog design verification and validation, a method includes receiving a recovered layout and a golden data for a design; extracting a recovered netlist from the recovered layout and a golden netlist from the golden data; converting the recovered netlist into a recovered graph and the golden netlist into a golden graph; partitioning the recovered graph and the golden graph; and determining an assurance metric by comparing the recovered graph and the golden graph.