Analog Functional Grouping With Hybrid Graph Pair Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing automated methods for analog circuit design struggle with accurate recognition of functional device pairs at the device level, leading to false positives and requiring manual validation, while existing GNN models lack generalization across different circuit topologies and do not provide categorical information on detected pairs.
Innovation Solution
A hybrid approach combining subgraph isomorphism and relational graph convolutional networks (RGCN) to detect and classify functional device pairs, using a relational GraphSAGE model for multi-class link prediction, and a hierarchy-aware GNN architecture with edge-conditioned convolution (ECC) and Circuit-GIN layers to model analog circuits at the transistor level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If subgraph isomorphism is used to detect functional device pairs, then categorical information is provided, but false positives increase
Solution Approach 1:
The patent introduces GNNs as an intermediary component between the circuit graph and the detection output. The GNN processes the graph representation and learns to distinguish true functional pairs from false positives, while the subgraph isomorphism provides categorical information as an additional feature to the GNN, combining the strengths of both approaches
Solution Approach 2:
The patent merges subgraph isomorphism with GNN-based detection by combining their outputs. The subgraph isomorphism results provide categorical information that is fed into the GNN framework, creating a hybrid approach that leverages both exact matching capabilities and learned pattern recognition to reduce false positives
2Productivity
If GNN models are used for symmetry detection, then computational efficiency is improved, but generalization across different circuit topologies is limited
Solution Approach 1:
The patent designs the GNN framework to be universal across different circuit topologies by using graph representations that capture essential structural features. The model is trained on diverse circuit data and uses learnable parameters that adapt to different topology types, enabling it to generalize from training circuits to unseen circuit configurations
Solution Approach 2:
The patent employs parameter changes by using learnable embedding vectors for different node and edge types in the circuit graph. These parameters are optimized during training to capture topology-specific patterns, allowing the model to adapt its behavior to different circuit architectures while maintaining the same underlying GNN framework
3Extent of automation
If device-level symmetry detection is performed, then functional pair recognition is achieved, but detection accuracy decreases compared to system-level
Solution Approach 1:
The patent incorporates feedback mechanisms where the GNN model learns from detection results and adjusts its predictions. The model receives feedback in the form of loss signals during training that guide parameter updates, and during inference, it can use confidence scores to identify cases requiring further validation, effectively learning from its own performance patterns
Data Source
AI summary
Methods, systems, and computer-readable media are used in graph-based machine learning of analog integrated circuits (ICs). In a first aspect, functional device pairs in transistor-level circuits are detected and classified using a hybrid approach combining a subgraph isomorphism algorithm, such as VF2, with a trained relational-graph convolutional network (RGCN). The VF2 algorithm identifies candidate pairs and initial categories, while the RGCN filters false positives using link prediction scores, preserving category labels for validated pairs. In a second aspect, a relational GraphSAGE model performs multi-class link prediction on a heterogeneous graph with netlist and functional relation edge types, labeling device pairs into analog primitive categories without technology-dependent features and merging overlapping pairs into larger functional groups. In a third aspect, circuit performance is predicted using a hierarchy-aware graph neural network comprising an edge-conditioned convolution (ECC) layer and multiple Circuit graph isomorphism network layers corresponding to hierarchy levels of device groupings.