Analog Head Switch Control for Low-Leakage Memory Sleep Modes

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Solution Overview

Problem

Integrated circuits with embedded memories face high power consumption and leakage issues due to varying operating modes, particularly when idle banks are powered by an elevated memory power supply voltage, leading to increased leakage currents.

Innovation Solution

Implementing an analog gate voltage driver to control head switch transistors in a partially on state during a 'light-sleep' mode, allowing banks to operate with a reduced power supply voltage, thereby reducing leakage currents while maintaining the memory power supply voltage at an elevated level for active banks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If head switch transistors are kept fully on to maintain data in bitcells, then data retention is ensured, but leakage current increases significantly

Engineering Contradiction:

Improvedata retentionVSAvoidleakage current

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies parameter changes by transitioning the head switch transistor gate voltage from a digital state (fully on or fully off) to an analog state (partially on). During light-sleep mode, the voltage regulator adjusts the gate voltage to an intermediate analog level, allowing the transistor to operate in its linear region rather than saturation or cutoff, thereby reducing leakage while maintaining data retention.

Inventive Principle:

Principle #35Parameter changes

2Speed

If memory power supply voltage is elevated for increased memory speed, then operating speed improves, but power consumption and leakage increase

Engineering Contradiction:

Improvememory speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamics by enabling the memory system to dynamically transition between different operating modes (active, retention, light-sleep, deep-sleep) with varying power supply voltages. The voltage regulator dynamically adjusts the gate voltage of head switch transistors based on the operational state, allowing the system to optimize between speed and power consumption in real-time.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the power supply voltage parameter from a fixed elevated level to a variable level that can be adjusted according to operational needs. During light-sleep mode, the gate voltage is reduced to an analog level that maintains sufficient operation for data retention while significantly reducing power consumption compared to the fully elevated active mode voltage.

Inventive Principle:

Principle #35Parameter changes

3Loss of energy

If head switch transistors are switched off to reduce power consumption, then leakage decreases, but data retention capability is lost

Engineering Contradiction:

Improvepower consumptionVSAvoiddata retention capability

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent applies parameter changes by using an analog gate voltage level that is intermediate between the fully on state (required for data retention) and the fully off state (required for minimal power consumption). This analog parameter setting allows the head switch transistor to maintain a conductive path sufficient for data retention while consuming significantly less power than the fully on state.

Inventive Principle:

Principle #35Parameter changes

4Ease of operation

If digital gate voltage control is used for head switch transistors, then control simplicity is maintained, but inability to achieve partial on state increases leakage

Engineering Contradiction:

Improvecontrol simplicityVSAvoidleakage current

Core Design Contradiction:

Ease of operationVSLoss of energy

Solution Approach 1:

The patent transitions from digital parameter control (discrete on/off states) to analog parameter control (continuous voltage levels). The voltage regulator generates an analog gate voltage that can be precisely adjusted to any level between the supply voltage and ground, enabling the head switch transistor to operate in a partially on state that reduces leakage while maintaining data retention.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces power consumption and leakage by enabling idle banks to operate with a retention-level power supply, enhancing battery life and transition speed without affecting active banks.

Implementation Method 1

a voltage regulator configured to regulate a gate voltage of the at least one head switch transistor during a light-sleep mode for the bitcell array

Methodology Applied

Scientific EffectVoltage regulation:

Data Source

PatentUS12620421B2Memory with reduced leakage through analog head switch control

Publication Date: 2026.05.05 QUALCOMM INC

AI summary

A memory is provided that includes an analog gate voltage driver that drives the gate of a head switch transistor for a bitcell array with an analog gate voltage while the bitcell array operates in a light-sleep mode. The analog gate voltage switches the head switch transistor partially on so that the head switch transistor passes a reduced power supply voltage despite being powered by a memory power supply voltage that is greater than the reduced power supply voltage. The reduced power supply voltage has a sufficient magnitude so that the bitcell array retains its stored binary contents during the light-sleep mode.